Semiconductor device

• US 9,716,180 B2
• Filed: 01/27/2016
• Issued: 07/25/2017
• Est. Priority Date: 09/15/2004
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Higaki, Yoshinari, Yamazaki, Shunpei, Sakakura, Masayuki
• Primary Examiner(s): Wong, Tina
• Application Number:
  US15/007,916
• Publication Number:
  US 20160204275A1
• Time in Patent Office: 545 Days
• Field of Search: None
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.

Claims

1. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating layer over the gate electrode;

a semiconductor layer over the gate insulating layer;

a first conductive layer comprising titanium, the first conductive layer being in contact with the semiconductor layer;

a second conductive layer on the first conductive layer;

a third conductive layer comprising an ITO over the second conductive layer, the third conductive layer being in contact with an end portion and part of a top surface of the second conductive layer; and

an insulating layer over the second conductive layer,

wherein the third conductive layer is in contact with the first conductive layer,

wherein a first width of the first conductive layer is larger than a second width of a top portion of the second conductive layer,

wherein the second conductive layer comprises a low-resistant metal,

wherein the semiconductor layer comprises an amorphous silicon,

wherein an extending portion of the third conductive layer is a pixel electrode, and

wherein the pixel electrode is provided over the insulating layer.

2. The semiconductor device according to claim 1,

wherein the gate electrode comprises tantalum nitride and tungsten.

3. The semiconductor device according to claim 1,

wherein the low-resistant metal comprises aluminum.

7. The semiconductor device according to claim 1,

wherein a portion in which the second conductive layer is in contact with the third conductive layer partly overlaps with the semiconductor layer.

4. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating layer over the gate electrode;

a semiconductor layer over the gate insulating layer;

a source electrode and a drain electrode, over the semiconductor layer;

wherein one of the source electrode and the drain electrode is electrically connected to the semiconductor layer, and has a first conductive layer and a second conductive layer;

a third conductive layer comprising an ITO over the second conductive layer, the third conductive layer being in contact with an end portion and part of a top surface of the second conductive layer,

an insulating layer over the source electrode and the drain electrode;

wherein the second conductive layer is provided on the first conductive layer,

wherein the third conductive layer is in contact with the first conductive layer,

wherein a first width of the first conductive layer is larger than a second width of a top portion of the second conductive layer,

wherein the first conductive layer comprises titanium,

wherein the second conductive layer comprises a low-resistant metal,

wherein the semiconductor layer comprises an amorphous silicon,

wherein an extending portion of the third conductive layer is a pixel electrode,

wherein the pixel electrode is provided over the insulating layer,

wherein an orientation film is provided over the pixel electrode, and

wherein a liquid crystal layer is provided over the orientation film.

5. The semiconductor device according to claim 4,

wherein the gate electrode comprises tantalum nitride and tungsten.

6. The semiconductor device according to claim 4,

wherein the low-resistant metal comprises aluminum.

8. The semiconductor device according to claim 4,

wherein a portion in which the second conductive layer is in contact with the third conductive layer partly overlaps with the semiconductor layer.