Real-time multi-functional ECG signal processing system, DSPE for the ECG signal processing system, and method thereof

• US 9,717,430 B2
• Filed: 06/12/2014
• Issued: 08/01/2017
• Est. Priority Date: 06/12/2013
• Status: Active Grant

• Current Assignee: Agency For Science Technology and Research (Government of Singapore)
• Original Assignee: Agency For Science Technology and Research (Government of Singapore)
• Inventors: Liu, Xin, Zhou, Jun
• Primary Examiner(s): NGUYEN, LINH V
• Application Number:
  US14/897,581
• Publication Number:
  US 20160135705A1
• Time in Patent Office: 1,146 Days
• Field of Search: 341139, 341141, 341142, 341155
• CPC Class Codes: A61B 5/30 Input circuits therefor
• CPC Class Codes: A61B 5/316 Modalities, i.e. specific diagnostic methods
• CPC Class Codes: A61B 5/366 Detecting abnormal QRS complex, e.g. widening
• CPC Class Codes: A61B 5/369 Electroencephalography [EEG] devices for psychotechnics A61B5/16
• CPC Class Codes: A61B 5/4812 Detecting sleep stages or cycles
• CPC Class Codes: A61B 5/4836 Diagnosis combined with treatment in closed-loop systems or methods A61B5/0036 takes precedence
• CPC Class Codes: A61B 5/7203 for noise prevention, reduction or removal
• CPC Class Codes: G01R 19/2509 Details concerning sampling, digitizing or waveform capturing

Abstract

An electrocardiogram (ECG) signal processing system is provided. The ECG signal processing system comprises an analog-to-digital converter (ADC) configured to convert an input analog ECG signal into a digital ECG signal, and a digital signal processing engine (DSPE) coupled to the ADC to receive the digital ECG signal. The DSPE is configured to decompose and reconstruct the digital ECG signal. A dynamic system clock source is coupled to the ADC and the DSPE for dynamic signal sampling, the dynamic system clock source clocking the ADC and the DSPE at a first frequency f1 to detect one or more first parameters of the input analog ECG signal and at a second frequency f2 to detect one or more second parameters of the input analog ECG signal.

Claims

1. An electrocardiogram (ECG) signal processing system, the ECG signal processing system comprising:

an analog-to-digital converter (ADC) operable for sampling an input analog ECG signal at a first frequency f₁ and a second frequency f₂ to convert the input analog ECG signal into a digital ECG signal;

a digital signal processing engine (DSPE) coupled to the ADC to receive the digital ECG signal, the DSPE being configured to sample the digital ECG signal at the first frequency f₁ and the second frequency f₂ to decompose and reconstruct the digital ECG signal; and

a dynamic system clock source coupled to the ADC and the DSPE for dynamic adaptive signal sampling, the dynamic system clock source clocking the ADC and the DSPE at the first frequency f₁ to detect one or more first parameters of the input analog ECG signal and at the second frequency f₂ to detect one or more second parameters of the input analog ECG signal, wherein the DSPE comprises;

a wavelet transformation (WT) unit, the WT unit comprising a plurality of scales, wherein the WT unit is adapted to decompose the digital ECG signal into a plurality of wavelets, each wavelet being output from one of the plurality of scales; and

a plurality of signal processing blocks, each of the signal processing blocks coupled to one or more outputs of the plurality of scales and configured to receive and process the one or more wavelets from the respective outputs, wherein the signal processing blocks provide processing functions which differ from one another, wherein the plurality of signal processing blocks comprise a cardiac features extraction block, the cardiac features extraction block receiving a high pass filtering of a predetermined one of the plurality of scales, wherein the cardiac features extraction block is configured to process a QRS complex extraction when the dynamic system clock source is clocking the ADC and the DSPE at the first frequency f₁, and to process P wave extraction and T wave extraction when the dynamic system clock source is clocking the ADC and the DSPE at the second frequency f₂.

2. The ECG signal processing system of claim 1, wherein the ECG signal processing system is configured to detect a QRS complex when f₁ is 500 Hz, and wherein the plurality of scales comprises six scales, the plurality of scales having 3 dB bandwidths of around 125 to 250 Hz;

62.5 to 125 Hz;

18 to 58.5 Hz;

8 to 27 Hz;

4 to 13.5 Hz; and

2 to 6.5 Hz for the first to the sixth scales respectively, when the dynamic system clock source is clocking at the first frequency f₁.

3. The ECG signal processing system of claim 1, wherein the ECG signal processing system is configured to detect P and T waves when f₂ is 250 Hz, and wherein the plurality of scales comprises six scales, the plurality of scales having 3 dB bandwidths of around 62.5 to 125 Hz;

18 to 58.5 Hz;

8 to 27 Hz, 4 to 13.5 Hz;

2 to 6.5 Hz; and

1 to 3.25 Hz for the first to the sixth scales respectively, when the dynamic system clock source is clocking at the second frequency f₂.

4. The ECG signal processing system of claim 1, wherein the WT unit comprises a plurality of low pass filters (LPF) and a plurality of high pass filters (HPF), and wherein the plurality of signal processing blocks further comprises a baseline drifting removal unit, the baseline drifting removal unit being coupled to the respective outputs of the high pass filters of the fifth and sixth scales and the output of the low pass filter of the sixth scale.

5. The ECG signal processing system of claim 4, wherein the dynamic system clock source is switched between f₁ and f₂ by a multiplexer, the multiplexer being controlled by a comparison between output of the high pass filter on the second scale and a threshold TH_f, and wherein the multiplexer switches to the first frequency f₁ when the output of the high pass filter on the second scale exceeds the threshold TH_f.

6. The ECG signal processing system of claim 4, wherein the predetermined one of the plurality of scales comprises the fourth scale, and wherein the cardiac features extraction block is coupled to the output of the high pass filter of the fourth scale.

7. The ECG signal processing system of claim 4, wherein the plurality of signal processing blocks comprise an ECG signal reconstruction block, and wherein the ECG signal reconstruction block is coupled to outputs of high pass filters of the first to the fourth scales and the outputs of the baseline drifting removal unit, wherein the ECG signal reconstruction block is configured to synchronize and output signals belonging to the high pass filtered components of the first to the sixth scales and the low pass filtered component of the sixth scale.

8. The ECG signal processing system of claim 1, wherein the ADC is a successive approximation (SAR) ADC.

9. A digital signal processing engine (DSPE) for ECG signal processing, the DSPE being coupled to a digital ECG signal input and comprising:

a wavelet transformation (WT) unit, the WT unit comprising a plurality of scales, wherein the WT unit is adapted to decompose the digital ECG signal into a plurality of wavelets, each wavelet being output from one of the plurality of scales; and

a plurality of signal processing blocks, each of the signal processing blocks coupled to one or more outputs of the plurality of scales and configured to receive and process the one or more wavelets from the respective outputs, wherein the signal processing blocks provide processing functions which differ from one another;

wherein the WT unit and the plurality of signal processing blocks are coupled to a dynamic system clock source for dynamic signal sampling, the dynamic system clock source clocking the DSPE at a first frequency f₁ to detect one or more first parameters of the input digital ECG signal and at a second frequency f₂ to detect one or more second parameters of the input digital ECG signal, wherein the dynamic system clock source is switched between f₁ and f₂ by a multiplexer, the multiplexer being con rolled by a comparison between an output of a high pass filter on a predetermined one of the plurality of scales and a threshold TH_f, wherein the multiplexer switches to the first frequency f₁ when the output of the high pass filter on the predetermined one of the plurality of scales exceeds the threshold TH_f.

10. The DSPE of claim 9, wherein the plurality of scales comprises a plurality of cascaded scales, each of the plurality of cascaded scales having a different bandwidth, and wherein a wavelet output from one of the cascaded scales is derived from a wavelet output from an earlier one of the plurality of cascaded scales.

11. A digital signal processing engine (DSPE) for ECG signal processing, the DSPE being coupled to a digital ECG signal input and comprising:

a wavelet transformation (WT) unit, the WT unit comprising a plurality of scales, wherein the WT unit is adapted to decompose the digital ECG signal into a plurality of wavelets, each wavelet being output from one of the plurality of scales; and

a plurality of signal processing blocks, each of the signal processing blocks coupled to one or more outputs of the plurality of scales and configured to receive and process the one or more wavelets from the respective outputs, wherein the signal processing blocks provide processing functions which differ from one another;

wherein the WT unit and the plurality of signal processing blocks are coupled to a dynamic system clock source for dynamic signal sampling, the dynamic system clock source clocking the DSPE at a first frequency f₁ to detect one or more first parameters of the input digital ECG signal and at a second frequency f₂ to detect one or more second parameters of the input digital ECG signal and wherein the WT unit comprises a plurality of low pass filters (LPF) and a plurality of high pass filters (HPF) and wherein the dynamic system clock source is switched between f₁ and f₂ by a multiplexer, the multiplexer being controlled by a comparison between an output of a high pass filter on a second one of the plurality of scales and a threshold TH_f, wherein the multiplexer switches to the first frequency f₁ when the output of the high pass filter on the second one of the plurality of scales exceeds the threshold TH_f.

12. The DSPE of claim 11, wherein the plurality of signal processing blocks comprise at least one noise suppression block.

13. The DSPE of claim 12, wherein each of the at least one noise suppression block comprises at least one threshold-based de-nosing unit, each of the at least one threshold-based de-nosing unit being coupled to one of the respective outputs of the WT unit emitting wavelets coupled to the first three of the plurality of scales, and wherein the output of a high pass filter smaller than an adaptive threshold is forced to zero.

14. A method for processing an ECG signal comprising:

providing a first device operable to sample an input ECG signal at a first frequency f₁ and a second frequency f₂ and configured to convert the input ECG analog signal into a digital ECG signal;

providing a second device coupled to the first device to receive the digital ECG signal, the second device being configured to sample the digital ECG signal at the first frequency f₁ and the second frequency f₂ to decompose and reconstruct the digital ECG signal; and

providing a dynamic clock source connected to the first and the second device, wherein the dynamic clock source clocks the first and the second devices at the first frequency f₁ to detect one or more first parameters of the input analog ECG signal and at the second frequency f₂ to detect one or more second parameters of the input analog ECG signal,

providing a wavelet transformation (WT) unit, the WT unit comprising a plurality of scales, wherein the WT unit is adapted to decompose the digital ECG signal into a plurality of wavelets, each wavelet being output of one of the plurality of scales;

providing a plurality of signal processing blocks, each of the sign processing blocks coupled to one or more outputs of the plurality of scales and configured to receive and process the one or more wavelets from the respective outputs, wherein the signal processing blocks provide processing function which differ from one another, and wherein the plurality of signal processing blocks comprise a cardiac features extraction block; and

the cardiac features extraction block receiving a high pass filtering of a predetermined one of the plurality of scales for extracting a QRS complexes when the dynamic system clock source is clocking the ADC and the DSPE at the first frequency f₁, and for extracting P waves and T waves when the dynamic system clock source is clocking the ADC and the DSPE at the second frequency f₂.

15. The method for processing the ECG signal of claim 14, wherein the method comprises detecting a QRS complex when f₁ is 500 Hz.

16. The method for processing the ECG signal of claim 14, wherein the method comprises detecting P and T waves when f₂ is 250 Hz.

17. The method for processing the ECG signal of claim 14, wherein the operation of providing the WT unit comprises providing a plurality of low pass filters (LPF), a plurality of high pass filters (HPF), and at least one storage unit.