Prefetching of discontiguous storage locations as part of transactional execution

• US 9,720,725 B2
• Filed: 08/20/2015
• Issued: 08/01/2017
• Est. Priority Date: 06/30/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Busaba, Fadi Y., Greiner, Dan F., Gschwind, Michael Karl, Schwarz, Eric M., Slegel, Timothy J., Michael, Maged M., Salapura, Valentina
• Primary Examiner(s): CHOE, YONG J
• Application Number:
  US14/830,908
• Publication Number:
  US 20150378781A1
• Time in Patent Office: 712 Days
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/314 In storage network, e.g. network attached cache
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence
• CPC Class Codes: G06F 9/528 by using speculative mechanisms

Abstract

Transactional execution of a transaction beginning instruction initiates prefetching, by a CPU, of discontiguous storage locations specified by a list. The list includes entries specifying addresses and may also include corresponding metadata. The list may be specified by levels of indirection. Fetching of corresponding discontiguous cache lines is initiated while in TX mode. Additional instructions in the transaction may be executed and use the prefetched cache lines.

Claims

1. A computer implemented method for prefetching data at discontiguous storage locations in a transactional execution (TX) environment, the method comprising:

executing a transaction-begin (TB) instruction for beginning execution, by a processor, of transactional execution (TX) of a transaction in a transactional mode, the executing the TB instruction causing initiating prefetching of memory data based on a list having a location specified by the TB instruction, the list having one or more entries, each entry of the list specifying a storage address of the memory data, each storage address corresponding to an address in a hierarchical cache structure comprising a main memory at a highest level and a local cache at a lowest level relative to a central processing unit of the computer system,

wherein the prefetching comprises;

initiating fetching, to cache lines of a cache, of the memory data corresponding to the addresses specified by the entries of the specified list.

2. The method of claim 1, wherein each entry of the list further specifies corresponding metadata indicating any one of usage of a block of memory and information about the list.

3. The method of claim 2, wherein each entry of the list comprises metadata indicating information about the list, the information about the list comprising any one of a size value of a block of memory, an address-space control (ASC) value for locating the block of memory, and a number of entries of the list.

4. The method of claim 2, wherein each entry of the list comprises metadata indicating usage of the block of memory, the usage comprising any one of exclusive, shared, read-only, and modified, and the blocks of memory comprise any one of instructions and data.

5. The method of claim 2, wherein the metadata comprises any one of a size value, a purpose value, and an address-space control (ASC) value, or a combination thereof, of the corresponding block of memory specified by the address of the corresponding entry.

6. The method of claim 1, wherein the location of the list specified by the TB instruction is any one of an address in memory and a range of registers.

7. The method of claim 1, wherein the location of the list specified by the TB instruction is associated with an address of a transaction diagnostic block of the TB instruction.