Configurable volatile memory without a dedicated power source for detecting a data save trigger condition

• US 9,721,660 B2
• Filed: 12/02/2014
• Issued: 08/01/2017
• Est. Priority Date: 10/24/2014
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Govindan, Sriram, Khessib, Badriddine, Kelly, Bryan, Andrewartha, J. Michael, Siegler, John J., Shaw, Mark A.
• Primary Examiner(s): Peyton, Tammara
• Application Number:
  US14/557,708
• Publication Number:
  US 20160118121A1
• Time in Patent Office: 973 Days
• Field of Search: 714 14, 714 22
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1456 Hardware arrangements for backup
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A volatile memory data save subsystem may include a coupling to a shared power source such as a chassis or rack battery, or generator. A data save trigger controller sends a data save command toward coupled volatile memory device(s) such as NVDIMMs and PCIe devices under specified conditions: a programmable amount of time passes without AC power, a voltage level drops below normal but is still sufficient to power the volatile memory device during a data save operation, the trigger controller is notified of an operating system shutdown command, or the trigger controller is notified of an explicit data save command without a system shutdown command. NVDIMMs can avoid reliance on dedicated supercapacitors and dedicated batteries. An NVDIMM may perform an asynchronous DRAM reset in response to the data save command. Voltage step downs may be coordinated among power supplies. After data is saved, power cycles and the system reboots.

Claims

1. A volatile memory data save subsystem for a motherboard in a system, the subsystem comprising:

a volatile memory device shared power source coupling that when coupled to a shared power source and also coupled to a volatile memory device by the motherboard, provides operating power to the volatile memory device, the volatile memory device being one of at least two separately pluggable devices that receive power from the shared power source;

a data save trigger coupling that when coupled to the volatile memory device and triggered, sends a data save command toward the volatile memory device; and

a data save trigger controller that operates to trigger the data save trigger coupling when at least one of the following conditions occur;

(a) a programmable amount of time passes with the volatile memory device being powered by a source which is not driven by an alternating current (“

AC”

) power source;

(b) a voltage level on the volatile memory device shared power source drops to a value that is less than normal operating power but is still sufficient to power the volatile memory device during a data save operation;

(c) the data save trigger controller is notified of an operating system shutdown command;

or

(d) the data save trigger controller is notified of an explicit data save command in the absence of an operating system shutdown command.

2. The volatile memory data save subsystem of claim 1, wherein the volatile memory device includes an non-volatile dual in-line memory module (“

NVDIMM”

), the volatile memory device shared power source coupling includes an NVDIMM slot, and the shared power source includes at least one of;

a chassis battery, a shared rack level battery system, a diesel generator, a natural gas generator, another generator.

3. The volatile memory data save subsystem of claim 1, wherein the volatile memory device includes an NVDIMM that has no dedicated supercapacitor and also has no dedicated battery.

4. The volatile memory data save subsystem of claim 1, wherein the volatile memory device includes a Peripheral Component Interconnect Express (“

PCIe”

) device, and the volatile memory device shared power source coupling includes a PCIe rail on the motherboard.

5. The volatile memory data save subsystem of claim 1, wherein the data save trigger controller operates to trigger the data save trigger coupling when the programmable amount of time passes with the volatile memory device being powered by a chassis battery, and the programmable amount of time was previously programmed based on a chassis battery power estimation.

6. The volatile memory data save subsystem of claim 1, wherein the data save trigger controller operates to trigger the data save trigger coupling when the power level on the volatile memory device shared power source drops below a 12V normal operating power to a level between 10.8V and 11.5V that is sufficient to power the volatile memory device during the data save operation.

7. The volatile memory data save subsystem of claim 1, wherein the data save trigger controller operates to trigger the data save trigger coupling when the data save trigger controller is notified of an explicit data save command in the absence of an operating system shutdown command.

8. A volatile memory data save subsystem for a motherboard in a server system, the subsystem comprising:

a frame having a power supply and a frame manager;

a plurality of volatile memory device power source couplings coupled to the frame power supply and to respective volatile memory device groups, each volatile memory device group including at least one volatile memory device;

a data save trigger coupling that when coupled to at least one of the volatile memory devices and triggered sends a data save command toward at least one of the volatile memory devices; and

a data save trigger controller that operates to trigger the data save trigger coupling when at least one of the following conditions occur;

(a) a programmable amount of time passes with the frame power supply not receiving alternative current (“

AC”

) power;

(b) the frame power supply drops output voltage to a value that is less than a normal operating level but is still sufficient to power the volatile memory device during a data save operation;

(c) the data save trigger controller is notified of an operating system shutdown command;

or

(d) the data save trigger controller is notified of an explicit data save command in the absence of an operating system shutdown command; and

wherein each of the volatile memory devices has no dedicated supercapacitor and also has no dedicated battery.

9. The volatile memory data save subsystem of claim 8, wherein at least a portion of the data save trigger controller resides in the frame manager.

10. The volatile memory data save subsystem of claim 8, wherein the volatile memory device power source couplings include at least one of the following:

an non-volatile dual in-line memory module (“

NVDIMM”

) slot, a Peripheral Component Interconnect Express (“

PCIe”

) rail.

11. The volatile memory data save subsystem of claim 8, wherein the frame includes a chassis, the power supply is a chassis power supply, and at least one of the volatile memory devices resides on a blade server that is coupled to the chassis.

12. The volatile memory data save subsystem of claim 8, wherein the frame includes a rack, the power supply is a rack power supply, and at least one of the volatile memory devices resides on a rack mounted server that is coupled to the rack.

13. The volatile memory data save subsystem of claim 8, wherein the frame data save trigger coupling is coupled to all of the volatile memory devices on the motherboard and when triggered sends a data save command toward all of the volatile memory devices.

14. A process for saving data despite power loss in a computing system having a main power supply and multiple memory devices couplable to a shared power source, each of the memory devices including a non-volatile dual in-line memory module (“

NVDIMM”

) with a volatile memory portion and a non-volatile memory portion and without a corresponding dedicated power source, wherein the process comprising;

detecting a data save trigger condition for the memory devices in the computing system,

the data save trigger condition including one or more of;

an output voltage of the main power supply is lowered to a value that is less than a normal operating level but is sufficient to power the memory device during a data save operation;

a notification of an operating system shutdown command is received;

or

an explicit data save command is received;

in response to detecting the data save trigger condition,

sending a data save command to one of the memory devices; and

providing power to the one of the memory devices from the shared power source, thereby allowing

the memory device to perform a data save operation to save data from a volatile memory portion of the memory device into a non-volatile memory portion of the memory device with the power provided from the shared power source.

15. The process of claim 14, wherein sending a data save signal includes dropping a power supply output to a value that is less than a normal operating power but is still sufficient to power the volatile memory device during the data save operation.

16. The process of claim 14, wherein providing power to the memory device from the shared power source includes coordinating a voltage step down.

17. The process of claim 14, further comprising performing an asynchronous dynamic random access memory (“

DRAM”

) reset at the NVDIMM in response to the data save command.

18. The process of claim 14, wherein providing power to the memory device includes maintaining power to a Peripheral Component Interconnect Express (“

PCIe”

) rail and/or a dual in-line memory module (“

DIMM”

) rail, and removing power after the data save operation is complete.

19. The process of claim 14, further comprising lowering the output wattage of the shared power source.

20. The process of claim 14, wherein after commanded data save operations are complete, removing power from the memory device and resetting the computing system.