Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control

• US 9,721,790 B2
• Filed: 06/01/2016
• Issued: 08/01/2017
• Est. Priority Date: 06/02/2015
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Atomera Incorporated
• Inventors: Stephenson, Robert John, Mears, Robert J., Cody, Nyles
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US15/169,983
• Publication Number:
  US 20160358773A1
• Time in Patent Office: 426 Days
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/151 Compositional structures H01L29/157 and H01L29/158 take precedence
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation

Abstract

A method for processing a semiconductor wafer in a single wafer processing chamber may include heating the single wafer processing chamber to a temperature in a range of 650-700° C., and forming at least one superlattice on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions. Depositing the oxygen may include depositing the oxygen using an N₂O gas flow.

Claims

1. A method for processing a semiconductor wafer in a single wafer processing chamber, the method comprising:

heating the single wafer processing chamber to a temperature in a range of 650-700°

C.; and

forming at least one superlattice on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;

wherein depositing the oxygen comprises depositing the oxygen using an N₂O gas flow, wherein the N₂O gas flow comprises 0.1% to 10% N₂O in a gas comprising He.

2. The method of claim 1 wherein depositing the oxygen comprises depositing the oxygen with an exposure time in a range of 1 to 100 seconds.

3. The method of claim 1 wherein the N₂O gas flow is in a range of 10 to 5000 standard cubic centimeters per minute (SCCM).

4. The method of claim 1 wherein depositing the oxygen comprises depositing the oxygen at a pressure in a range of 10 to 100 Torr.

5. The method of claim 1 wherein a total dose of N₂O is in a range of 1×

10¹⁴ to 7×

10¹⁴ atoms/cm² during the oxygen monolayer formation.

6. The method of claim 1 wherein the semiconductor wafer comprises a plurality of spaced apart shallow trench isolation (STI) regions, and wherein forming the at least one superlattice comprises selectively forming a respective superlattice between adjacent pairs of STI regions.

7. The method of claim 1 wherein forming the at least one superlattice comprises a blanket superlattice formation on the semiconductor wafer.

8. The method of claim 1 wherein at least some silicon atoms from opposing base silicon portions are chemically bound together through the at least one oxygen monolayer therebetween.

9. A method for processing a semiconductor wafer in a single wafer processing chamber, the semiconductor wafer comprising a plurality of spaced apart shallow trench isolation (STI) regions, the method comprising:

heating the single wafer processing chamber to a temperature in a range of 650-700°

C.; and

selectively forming a respective superlattice between adjacent pairs of STI regions on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;

wherein depositing the oxygen comprises depositing the oxygen using an N₂O gas flow and at a pressure in a range of 10 to 100 Torr, and wherein the N₂O gas flow comprises 0.1% to 10% N₂O in a gas comprising He.

10. The method of claim 9 wherein depositing the oxygen comprises depositing the oxygen with an exposure time in a range of 1 to 100 seconds.

11. The method of claim 9 wherein the N₂O gas flow is in a range of 10 to 5000 standard cubic centimeters per minute (SCCM).

12. The method of claim 9 wherein a total dose of N₂O is in a range of 1×

10¹⁴ to 7×

10¹⁴ atoms/cm² during the oxygen monolayer formation.

13. The method of claim 9 wherein at least some silicon atoms from opposing base silicon portions are chemically bound together through the at least one oxygen monolayer therebetween.

14. A method for processing a semiconductor wafer in a single wafer processing chamber, the method comprising:

heating the single wafer processing chamber to a temperature in a range of 650-700°

C.; and

forming a blanket superlattice on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;

wherein depositing the oxygen comprises depositing the oxygen using an N₂O gas flow and at a pressure in a range of 10 to 100 Torr, and wherein the N₂O gas flow comprises 0.1% to 10% N₂O in a gas comprising He.

15. The method of claim 14 wherein depositing the oxygen comprises depositing the oxygen with an exposure time in a range of 1 to 100 seconds.

16. The method of claim 14 wherein the N₂O gas flow is in a range of 10 to 5000 standard cubic centimeters per minute (SCCM).

17. The method of claim 14 wherein a total dose of N₂O is in a range of 1×

10¹⁴ to 7×

10¹⁴ atoms/cm² during the oxygen monolayer formation.

18. The method of claim 14 wherein at least some silicon atoms from opposing base silicon portions are chemically bound together through the at least one oxygen monolayer therebetween.

19. A method for processing a semiconductor wafer in a single wafer processing chamber, the method comprising:

heating the single wafer processing chamber to a temperature in a range of 650-700°

C.; and

forming at least one superlattice on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;

wherein depositing the oxygen comprises depositing the oxygen using an N₂O gas flow, and wherein the N₂O gas flow comprises 0.1% to 10% N₂O in a gas comprising Ar.

20. The method of claim 19 wherein depositing the oxygen comprises depositing the oxygen with an exposure time in a range of 1 to 100 seconds.

21. The method of claim 19 wherein the N₂O gas flow is in a range of 10 to 5000 standard cubic centimeters per minute (SCCM).

22. The method of claim 19 wherein depositing the oxygen comprises depositing the oxygen at a pressure in a range of 10 to 100 Torr.

23. The method of claim 19 wherein a total dose of N₂O is in a range of 1×

10¹⁴ to 7×

10¹⁴ atoms/cm² during the oxygen monolayer formation.

24. The method of claim 19 wherein the semiconductor wafer comprises a plurality of spaced apart shallow trench isolation (STI) regions, and wherein forming the at least one superlattice comprises selectively forming a respective superlattice between adjacent pairs of STI regions.

25. The method of claim 19 wherein forming the at least one superlattice comprises a blanket superlattice formation on the semiconductor wafer.

26. The method of claim 19 wherein at least some silicon atoms from opposing base silicon portions are chemically bound together through the at least one oxygen monolayer therebetween.

27. A method for processing a semiconductor wafer in a single wafer processing chamber, the method comprising:

heating the single wafer processing chamber to a temperature in a range of 650-700°

C.; and

forming at least one superlattice on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;

wherein depositing the oxygen comprises depositing the oxygen using an N₂O gas flow, and wherein a total dose of N₂O is in a range of 1×

10¹⁴ to 7×

10¹⁴ atoms/cm² during the oxygen monolayer formation.

28. The method of claim 27 wherein depositing the oxygen comprises depositing the oxygen with an exposure time in a range of 1 to 100 seconds.

29. The method of claim 27 wherein the N₂O gas flow is in a range of 10 to 5000 standard cubic centimeters per minute (SCCM).

30. The method of claim 27 wherein depositing the oxygen comprises depositing the oxygen at a pressure in a range of 10 to 100 Torr.

31. The method of claim 27 wherein the semiconductor wafer comprises a plurality of spaced apart shallow trench isolation (STI) regions, and wherein forming the at least one superlattice comprises selectively forming a respective superlattice between adjacent pairs of STI regions.

32. The method of claim 27 wherein forming the at least one superlattice comprises a blanket superlattice formation on the semiconductor wafer.

33. The method of claim 27 wherein at least some silicon atoms from opposing base silicon portions are chemically bound together through the at least one oxygen monolayer therebetween.