Wafer-level chip-scale package device having bump assemblies configured to furnish shock absorber functionality

• US 9,721,912 B2
• Filed: 03/04/2014
• Issued: 08/01/2017
• Est. Priority Date: 11/02/2011
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Khandekar, Viren, Thambidurai, Karthik, Sridharan, Vivek S.
• Primary Examiner(s): ENAD, CHRISTINE A
• Application Number:
  US14/195,946
• Publication Number:
  US 20150008576A1
• Time in Patent Office: 1,246 Days
• Field of Search: 257737, 438121
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/03828 Applying flux
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/119 Methods of manufacturing bump connectors involving a specific sequence of method steps
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/13561 On the entire surface of the core, i.e. integral coating
• CPC Class Codes: H01L 2224/13582 Two-layer coating
• CPC Class Codes: H01L 2224/13583 Three-layer coating
• CPC Class Codes: H01L 2224/136 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14131 : being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/14179 : Corner adaptations, i.e. disposition of the bump connectors at the corners of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/14505 : Bump connectors having different materials
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

Semiconductor devices are described that have bump assemblies configured to furnish shock absorber functionality. In an implementation, a wafer-levelchip-scale package devices include an integrated circuit chip having an array of bump assemblies disposed over the integrated circuit chip. The array of bump assemblies comprises a plurality of first bump assemblies that include solder bumps composed at least substantially of a solder composition (i.e., solder bumps that do not include a core). The array further comprises a plurality of second bump assemblies that includes a solder bump having a core configured to furnish shock absorber functionality to the integrated circuit chip.

Claims

1. A wafer-level chip-scale package device comprising:

an integrated circuit chip; and

an array of bump assemblies disposed directly on the integrated circuit chip, the array of bump assemblies comprising a plurality of first bump assemblies including solder bumps, where the solder bumps are without a core and are for electrical interconnection with a redistribution layer of the integrated circuit chip, composed at least substantially of a solder composition and a plurality of second bump assemblies including a solder bump having a plastic core configured to furnish shock absorber functionality to the integrated circuit chip, where the plurality of second bump assemblies is disposed about the perimeter of the integrated circuit chip and is not electrically interconnected with the integrated circuit chip, and where the plurality of first bump assemblies includes a first solder composition and the plurality of second bump assemblies includes a second solder composition different from the first solder composition.

2. The wafer-level chip-scale package device as recited in claim 1, wherein the plurality of second bump assemblies is disposed proximate to at least one edge of the integrated circuit chip.

3. The wafer-level chip-scale package device as recited in claim 1, wherein the core comprises a Divinylbenzene cross-linked co-polymer.

4. The wafer-level chip-scale package device as recited in claim 1, wherein the core has a diameter and the diameter of the core ranges from about 100 μ

m to about 350 μ

m.

5. The wafer-level chip-scale package device as recited in claim 1, wherein the integrated circuit chip comprises bonding pads and the bump assemblies comprise bump interfaces configured to furnish an interface boundary between the solder bumps and bonding pads.

6. The wafer-level chip-scale package device as recited in claim 5, wherein the bump interfaces comprise under bump metallization (UBM).

7. An electronic device comprising:

a printed circuit board; and

a wafer-level package device coupled to the printed circuit board, the waver-level package device comprising an integrated circuit chip having an array of bump assemblies disposed directly on the integrated circuit chip, the array of bump assemblies comprising a plurality of first bump assemblies having solder bumps, where the solder bumps are without a core and for electrical interconnection with a redistribution layer of the integrated circuit chip, composed at least substantially of a solder composition and a plurality of second bump assemblies including a solder bump having a plastic core configured to furnish shock absorber functionality to the integrated circuit chip, where the plurality of second bump assemblies is disposed about the perimeter of the integrated circuit chip and is not electrically interconnected with the integrated circuit chip, and where the plurality of first bump assemblies includes a first solder composition and the plurality of second bump assemblies includes a second solder composition different from the first solder composition.

8. The electronic device as recited in claim 7, wherein the plurality of second bump assemblies is disposed proximate to at least one edge of the integrated circuit chip.

9. The electronic device as recited in claim 7, wherein the core comprises a Divinylbenzene cross-linked co-polymer.

10. The electronic device as recited in claim 7, wherein the core has a diameter and the diameter of the core ranges from about 100 μ

m to about 350 μ

m.

11. The electronic device as recited in claim 7, wherein the integrated circuit chip comprises bonding pads and the bump assemblies comprise bump interfaces configured to provide an interface boundary between the solder bumps and bonding pads.

12. The electronic device as recited in claim 11, wherein the bump interfaces comprise under bump metallization (UBM).