Backside coupled symmetric varactor structure

• US 9,721,946 B2
• Filed: 10/19/2016
• Issued: 08/01/2017
• Est. Priority Date: 09/14/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc., Qualcomm Technologies Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm, Inc.
• Inventors: Lan, Je-Hsiung Jeffrey, Yun, Changhan Hobie, Kim, Jonghae, Kim, Daeik Daniel, Berdy, David Francis
• Primary Examiner(s): Tran, Dzung
• Application Number:
  US15/298,124
• Publication Number:
  US 20170077093A1
• Time in Patent Office: 286 Days
• Field of Search: 257602
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 27/0808 Varactor diodes
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66174 Capacitors with PN or Schottky junction, e.g. varactors capacitors with PN junction combined with MOS control H01L29/66189
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/93 Variable capacitance diodes, e.g. varactors

Abstract

A symmetric varactor structure may include a first varactor component. The first varactor component may include a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor. In addition, doped regions may surround the body of the first varactor component. The first varactor component may be supported on a backside by an isolation layer. The symmetric varactor structure may also include a second varactor component electrically coupled to the backside of the first varactor component through a backside conductive layer.

Claims

1. A method of fabricating a symmetric varactor structure, comprising:

fabricating a first varactor component adjacent to a second varactor component of the symmetric varactor structure on an isolation layer;

thinning the symmetric varactor structure to expose a body of the first varactor component and a body of the second varactor component;

depositing and patterning a conductive layer to couple the body of the first varactor component and the body of the second varactor component; and

then

depositing and patterning a passivation layer on a backside surface of the isolation layer and the conductive layer.

2. The method of claim 1, in which depositing and patterning the conductive layer further comprises:

depositing and patterning a redistribution layer as the conductive layer to couple the body of the first varactor component and the body of the second varactor component.

3. The method of claim 1, further comprising bonding a substrate to only the passivation layer.

4. The method of claim 1, further comprising incorporating the symmetric varactor structure into a chip, the chip integrated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

9. The method of claim 1, further comprising forming a shallow trench isolation region on the isolation layer, separating the first varactor component from a first doped region of the second varactor component.

5. A method of fabricating a symmetric varactor structure, comprising:

a step for fabricating a first varactor component adjacent to a second varactor component of the symmetric varactor structure on an isolation layer;

a step for thinning the symmetric varactor structure to expose a body of the first varactor component and a body of the second varactor component;

a step for depositing and patterning a conductive layer to couple the body of the first varactor component and the body of the second varactor component; and

then

a step for depositing and patterning a passivation layer on a backside surface of the isolation layer and the conductive layer.

6. The method of claim 5, in which the step for depositing and patterning the conductive layer further comprises:

a step for depositing and patterning a redistribution layer as the conductive layer to couple the body of the first varactor component and the body of the second varactor component.

7. The method of claim 5, further comprising a step for bonding a substrate to only the passivation layer.

8. The method of claim 5, further comprising a step for incorporating the symmetric varactor structure into a chip, the chip integrated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

10. The method of claim 5, further comprising a step for forming a shallow trench isolation region on the isolation layer, separating the first varactor component from a first doped region of the second varactor component.