Semiconductor devices having gate patterns in trenches with widened openings

• US 9,721,952 B2
• Filed: 03/23/2016
• Issued: 08/01/2017
• Est. Priority Date: 05/11/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Seo, Kwang-You, Kim, Ju-Youn
• Primary Examiner(s): Ingham, John C
• Assistant Examiner(s): MAZUMDER, DIDARUL A
• Application Number:
  US15/077,941
• Publication Number:
  US 20160204109A1
• Time in Patent Office: 496 Days
• Field of Search: 257347, 257E21202, 257E21204, 257E21251, 257E21252, 257E21409, 257E21432, 257E21444, 257E29158, 257E2916, 257E29266, 257E29345, 257402, 438197, 438402
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench.

Claims

1. A semiconductor device comprising:

a substrate;

a first interlayer insulating film disposed in a first region of the substrate and including a first trench;

a second interlayer insulating film disposed in a second region of the substrate and including a second trench;

a first gate insulating film formed along sidewalls and a bottom surface of the first trench;

a second gate insulating film formed along sidewalls and a bottom surface of the second trench;

a first work function adjusting film disposed in the first trench and including a bottom portion and sidewall portions extending upwardly from the bottom portion, the first work function adjusting film being disposed on sidewalls and a bottom surface of the first gate insulating film;

a second work function adjusting film disposed in the second trench and including a bottom portion and sidewall portions extending upwardly from the bottom portion, the second work function adjusting film being disposed on sidewalls and a bottom surface of the second gate insulating film;

a first adhesive film disposed in the first trench;

a second adhesive film disposed in the second trench;

a first metal gate pattern disposed on the first adhesive film and filling the first trench; and

a second metal gate pattern disposed on the second adhesive film and filling the second trench,

wherein an uppermost surface of the second metal gate pattern is higher above the substrate than is an uppermost surface of the second work function adjusting film.

2. The semiconductor device of claim 1, wherein a top portion of the first metal gate pattern is wider than a bottom portion of the first metal gate pattern, and

a top portion of the second metal gate pattern is wider than a bottom portion of the second metal gate pattern.

3. The semiconductor device of claim 1, wherein a width of a bottom portion of the first metal gate pattern is greater than a width of a bottom portion of the second metal gate pattern.

4. The semiconductor device of claim 1, wherein a height of the first metal gate pattern is greater than a height of the second metal gate pattern.

5. The semiconductor device of claim 1, wherein

each of the sidewall portions of the first work function adjusting film having a chamfered top surface, and

each of the sidewall portions of the second work function adjusting film having a chamfered top surface.

6. The semiconductor device of claim 1, wherein the first adhesive film is disposed on the chamfered top surface of each of the sidewall portions of the first work function adjusting film, and

the second adhesive film is disposed on the chamfered top surface of each of the sidewall portions of the second work function adjusting film.

7. The semiconductor device of claim 1, wherein each of the first gate insulating film and the second gate insulting film includes a high-k dielectric material.

8. The semiconductor device of claim 5, wherein each sidewall portion of the first work function adjusting film has an inner sidewall and an outer sidewall, and the chamfered top surface comprises an inclined top portion that connects the inner sidewall to the outer sidewall of each sidewall portion, wherein an uppermost surface of the first gate insulating film is higher above the substrate than is an uppermost surface of the inner sidewall of each side portion of the first work function adjusting film.

9. The semiconductor device of claim 1, wherein the first work function adjusting film comprises a first material and the second work function adjusting film comprises a second material that is different from the first material.

10. The semiconductor device of claim 9, wherein the first adhesive film directly contacts the first metal gate pattern and the second adhesive film directly contacts the second metal gate pattern.

11. A semiconductor device comprising:

a substrate;

a first interlayer insulating film disposed in a first region of the substrate and including a first trench;

a second interlayer insulating film disposed in a second region of the substrate and including a second trench;

a first gate insulating film formed along sidewalls and a bottom surface of the first trench;

a second gate insulating film formed along sidewalls and a bottom surface of the second trench;

a first N-type work function adjusting film disposed in the first trench;

a P-type work function adjusting film disposed in the second trench;

a second N-type work function adjusting film disposed in the second trench and disposed on the P-type work function adjusting film;

a first adhesive film disposed in the first trench;

a second adhesive film disposed in the second trench;

a first metal gate pattern disposed on the first adhesive film and filling the first trench; and

a second metal gate pattern disposed on the second adhesive film and filling the second trench,

wherein a top portion of the first metal gate pattern is wider than a bottom portion of the first metal gate pattern,

a top portion of the second metal gate pattern is wider than a bottom portion of the second metal gate pattern, and

wherein the second adhesive film covers an uppermost surface of the second N-type work function adjusting film.

12. The semiconductor device of claim 11, wherein the first adhesive film includes a bottom portion, sidewall portions and upper portions, the upper portions of the first adhesive film obliquely upwardly extending from the sidewall portions of the first adhesive film such that a distance between the upper portions of the first adhesive film is greater than a distance between the sidewall portions of the first adhesive film, and

the second adhesive film includes a bottom portion, sidewall portions and upper portions, the upper portions of the second adhesive film obliquely upwardly extending from the sidewall portions of the second adhesive film such that a distance between the upper portions of the second adhesive film is greater than a distance between the sidewall portions of the second adhesive film.

13. The semiconductor device of claim 11, wherein a width of the bottom portion of the first metal gate pattern is greater than a width of the bottom portion of the second metal gate pattern.

14. The semiconductor device of claim 11, wherein a height of the first metal gate pattern is greater than a height of the second metal gate pattern.

15. The semiconductor device of claim 11, wherein an uppermost surface of the second metal gate pattern is higher above the substrate than is the uppermost surface of the second N-type work function adjusting film.

16. A semiconductor device comprising:

a substrate;

a first interlayer insulating film disposed in a first region of the substrate and including a first trench;

a second interlayer insulating film disposed in a second region of the substrate and including a second trench;

a first gate insulating film formed along sidewalls and a bottom surface of the first trench;

a second gate insulating film formed along sidewalk and a bottom surface of the second trench;

a first adhesive film disposed in the first trench;

a second adhesive film disposed in the second trench, the second adhesive film comprising the same material as the first adhesive film;

a first metal gate pattern disposed on the first adhesive film and filling the first trench;

a second metal gate pattern disposed on the second adhesive film and filling the second trench;

first spacers formed on outer sidewalls of the first gate insulating film; and

second spacers formed on outer sidewalls of the second gate insulating film,

wherein a width of a bottom portion of the first meta gate pattern is greater than a width of a bottom portion of the second metal gate pattern, and

upper surfaces of the first spacers and an uppermost surface of the first metal gate pattern are coplanar with each other, and

upper surfaces of the second spacers and an uppermost surface of the second metal gate pattern are coplanar with each other,

wherein the uppermost surface of the second metal gate pattern is higher above the substrate than is an uppermost surface of an N-type work function adjusting film that is disposed in the second trench.

17. The semiconductor device of claim 16, wherein the semiconductor device is a fin type transistor.

18. The semiconductor device of claim 16, further comprising:

a first etch stop film disposed on the first gate insulating film; and

a second etch stop film disposed on the second gate insulating film.

19. The semiconductor device of claim 16, wherein the uppermost surface of the first metal gate pattern is wider than a bottom surface of the first metal gate pattern, and

the uppermost surface of the second metal gate pattern is wider than a bottom surface of the second metal gate pattern.