Structure and method for SRAM FinFET device having an oxide feature

• US 9,721,955 B2
• Filed: 04/25/2014
• Issued: 08/01/2017
• Est. Priority Date: 04/25/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Fung, Ka-Hing, Chang, Chih-Sheng, Wu, Zhiqiang
• Primary Examiner(s): Pizarro, Marcos D
• Application Number:
  US14/262,378
• Publication Number:
  US 20150311212A1
• Time in Patent Office: 1,194 Days
• Field of Search: 257192
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having an n-type FinFET (NFET) region and a p-type FinFET (PFET) region. The device also includes a first and a second fin structures over the substrate in the NFET region and a third fin structure over the substrate in the PFET region. The device also includes a first high-k (HK)/metal gate (MG) stack in the NFET region, including wrapping over a portion of the first fin structure, a first subset of the first source/drain (S/D) features, adjacent to the first HK/MG stack, over the recessed first fin structure and a second subset of the first S/D features partially over the recessed second fin structure and partially over the recessed first fin structure.

Claims

1. A transistor device comprising:

a substrate having an n-type fin field-effect transistor (NFET) region and a p-type fin field-effect transistor (PFET) region;

a first fin structure in the NFET region, the first fin structure including;

a first semiconductor material layer as its upper portion;

a second semiconductor material layer as its lower portion; and

an oxide layer on a side surface of its lower portion;

a second fin structure in the NFET region, the second fin structure including;

the first semiconductor material layer as its upper portion; and

the second semiconductor material layer as its lower portion, wherein the second fin structure joins the first fin structure and is free of the oxide layer;

a third fin structure over the substrate in the PFET region, the third fin structure including;

a third semiconductor material layer as its upper portion;

the first semiconductor material layer as its middle portion; and

the second semiconductor material layer as its bottom portion, wherein the third fin structure is free of the oxide layer;

a first source/drain (S/D) feature disposed over the first fin structure;

a second S/D feature disposed over both the first and second fin structures; and

at least two high-k/metal gate (HK/MG) stacks disposed over the first fin structure, wherein one of the HK/MG stacks is disposed between the first and second S/D features.

2. The device of claim 1, wherein the second fin structure is free of gate stacks directly above.

3. The device of claim 1, further comprising a fourth fin structure disposed over the substrate in the NFET region, wherein the fourth fin structure includes:

the first semiconductor material layer as its upper portion;

the second semiconductor material layer as its lower portion; and

the oxide layer on a side surface of its lower portion, wherein the second S/D feature is further disposed over the fourth fin structure.

4. A fin field-effect transistor (FinFET) device comprising:

a substrate having an n-type fin field-effect transistor (NFET) region and a p-type fin field-effect transistor (PFET) region;

a first fin structure over the substrate in the NFET region, the first fin structure including;

a first semiconductor material layer as its upper portion;

a second semiconductor material layer as its lower portion; and

an oxide layer on a side surface of its lower portion;

a second fin structure over the substrate in the NFET region, the second fin structure including;

the first semiconductor material layer as its upper portion; and

the second semiconductor material layer as its lower portion, wherein the second fin structure joins the first fin structure and is free of the oxide layer;

a third fin structure over the substrate in the PFET region, the third fin structure including;

a third semiconductor material layer as its upper portion;

the first semiconductor material layer as its middle portion; and

the second semiconductor material layer as its bottom portion;

a first source/drain (S/D) feature over the first fin structure;

a second S/D feature over both the second fin structure, and the first fin structure.

5. The device of claim 4, wherein a width of a portion of the first fin structure underneath the second S/D features is 10% to 25% of a width of the second S/D feature.

6. The device of claim 4, wherein the second fin structure is free of gate stacks directly above.

7. The device of claim 4, further comprising:

at least two HK/MG stacks wrapping at least a portion of the upper portion of the first fin structure.

8. The device of claim 7, wherein the HK/MG stacks are disposed above the oxide layer.

9. The device of claim 4, further comprising a fourth fin structure disposed over the substrate in the NFET region, wherein the fourth fin structure includes:

the first semiconductor material layer as its upper portion;

the second semiconductor material layer as its lower portion; and

the oxide layer on a side surface of its lower portion, wherein the second fin structure joins both the first and fourth fin structures.

10. The device of claim 9, wherein the second S/D feature is also disposed over the fourth fin structure.

11. The device of claim 10, wherein:

the first semiconductor material layer includes silicon;

the second semiconductor material layer includes silicon germanium;

the oxide layer includes silicon germanium oxide; and

the third semiconductor material layer includes silicon germanium.

12. A fin field-effect transistor (FinFET) device comprising:

a substrate having an n-type FinFET (NFET) region and a p-type FinFET (PFET) region;

a first fin structure over the substrate in the NFET region, the first fin structure including;

a first semiconductor material layer as its upper portion;

a second semiconductor material layer as its lower portion; and

an oxide layer on a side surface of its lower portion;

a second fin structure disposed over the substrate in the NFET region and joining the first fin structure, wherein the first and second fin structures have different compositions;

a third fin structure disposed over the substrate in the PFET region;

at least two first high-k (HK)/metal gate (MG) stacks disposed above the oxide layer and at least partially wrapping the upper portion of the first fin structure;

first source/drain (S/D) features disposed adjacent to the first HK/MG stacks, wherein a first one of the first S/D features is disposed over the first fin structure and a second one of the first S/D features is disposed over both the second fin structure and a first portion of the first fin structure;

a second HK/MG stack disposed over the third fin structure; and

a second S/D feature, disposed adjacent to the second HK/MG stack and over the third fin structure.

13. The device of claim 12, wherein the second fin structure includes:

the first semiconductor material as its upper portion; and

the second semiconductor material layer as its lower portion.

14. The device of claim 12, wherein the third fin structure includes:

a third semiconductor material layer as its upper portion;

the first semiconductor material layer as its middle portion; and

the second semiconductor material layer as its bottom portion.

15. The device of claim 12, wherein a width of the first portion of the first fin structure is 10% to 25% of a width of the second one of the first S/D features.

16. The device of claim 12, wherein:

the first semiconductor material layer includes silicon;

the second semiconductor material layer includes silicon germanium; and

the oxide layer includes silicon germanium oxide.

17. The device of claim 12, wherein the second one of the first S/D features is disposed over an entire width of the second fin structure.

18. The device of claim 12, wherein the second fin structure is free of the oxide layer.

19. The device of claim 12, further comprising a fourth fin structure disposed over the substrate in the NFET region, wherein the fourth fin structure includes:

the first semiconductor material layer as its upper portion;

the second semiconductor material layer as its lower portion; and

the oxide layer on a side surface of its lower portion, wherein the second fin structure joins both the first and fourth fin structures.

20. The device of claim 19, wherein the second one of the first S/D features is also disposed over a second portion of the fourth fin structure.

21. The device of claim 20, wherein the first portion of the first fin structure and the second portion of the fourth fin structure have about the same width.