Data line arrangement and pillar arrangement in apparatuses

• US 9,721,960 B2
• Filed: 03/13/2015
• Issued: 08/01/2017
• Est. Priority Date: 03/13/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Primary Examiner(s): Monbleau, Davienne
• Assistant Examiner(s): Cruz, Leslie Pilar
• Application Number:
  US14/656,980
• Publication Number:
  US 20160268280A1
• Time in Patent Office: 872 Days
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Some embodiments include an apparatus having semiconductor pillars in a modified hexagonal packing arrangement. The modified hexagonal packing arrangement includes a repeating pattern having at least portions of 7 different pillars. Each of the 7 different pillars is immediately adjacent to six neighboring pillars. A distance to two of the six neighboring pillars is a short distance, d_s; and a distance to four of the six neighboring pillars is a long distance, d_l. Some embodiments include an apparatus having semiconductor pillars in a packing arrangement. The packing arrangement comprises alternating first and second rows, with pillars in the first rows being laterally offset relative to pillars in the second rows. A distance between neighboring pillars in a common row as one another is a short distance, d_s, and a distance between neighboring pillars that are not in common rows as one another is a long distance, d_l.

Claims

1. An apparatus comprising:

semiconductor pillars in a modified hexagonal packing arrangement;

the modified hexagonal packing arrangement comprising a repeating pillar pattern, with the repeating pillar pattern having at least portions of 7 different pillars of said semiconductor pillars;

each of the different semiconductor pillars in a respective one of the repeating pillar patterns being immediately adjacent to six neighboring of said semiconductor pillars;

a distance from a central pillar to two of the six neighboring semiconductor pillars being a short distance, d_s; and

a distance from the central pillar to four of the six neighboring semiconductor pillars being a long distance, d_l;

with d_l being greater than d_s; and

a plurality of data lines extending across the modified hexagonal packing arrangement; and

wherein each of the different semiconductor pillars in a respective one of the repeating pillar patterns is electrically coupled to a different data line of the plurality of data lines.

2. The apparatus of claim 1 wherein d_l is at least about 1.1 times d_s.

3. The apparatus of claim 1 wherein d_l is at least about 1.3 times d_s.

4. The apparatus of claim 1 wherein d_l is at least about 1.5 times d_s.

5. The apparatus of claim 1 wherein the semiconductor pillars are substantially circular-shaped when viewed from above.

6. The apparatus of claim 1 wherein the semiconductor pillars are substantially elliptical-shaped when viewed from above.

7. The apparatus of claim 1 wherein the semiconductor pillars are substantially oval-shaped when viewed from above.

8. The apparatus of claim 1 wherein the semiconductor pillars comprise silicon.

9. The apparatus of claim 1 wherein the semiconductor pillars comprise polysilicon at least partially surrounding a dielectric material.

10. An apparatus comprising:

semiconductor pillars in a packing arrangement;

the packing arrangement comprising alternating first and second rows of the semiconductor pillars, with the semiconductor pillars in the first rows being laterally offset relative to the semiconductor pillars in the second rows;

a distance between neighboring of the semiconductor pillars in a common row as one another being a short distance, d_s, and a distance between neighboring of the semiconductor pillars that are not in common rows as one another being a long distance, d_l;

with d_l being greater than d_s;

the first and second rows extending along a first direction;

the distance d_l being along columns that extend along a second direction which intersects the first direction; and

a plurality of data lines extending across the semiconductor pillars;

the data lines extending along a third direction which is offset from the first direction by less than 90degrees, and which is substantially orthogonal to the second direction.

11. The apparatus of claim 10 wherein the packing arrangement is a modified hexagonal packing arrangement;

and wherein the modified hexagonal packing arrangement comprises a repeating pillar pattern, with the repeating pillar pattern having at least portions of 7 different pillars of said semiconductor pillars.

12. The apparatus of claim 10 wherein d_l is within a range of from about 1.1 times d_s to about 5 times d_s.

13. The apparatus of claim 10 wherein the semiconductor pillars are substantially vertical.

14. The apparatus of claim 10 wherein the data lines comprise bitlines.

15. The apparatus of claim 10 wherein at least some of the semiconductor pillars are substantially elliptical-shaped or substantially oval-shaped when viewed from above.

16. An apparatus comprising:

semiconductor pillars in a modified hexagonal packing arrangement;

the modified hexagonal packing arrangement comprising a repeating pillar pattern, with the repeating pillar pattern having at least portions of 7 different of said semiconductor pillars, each of the different semiconductor pillars in a respective one of the repeating pillar patterns being immediately adjacent to six neighboring semiconductor pillars;

a distance from a central pillar to two of the six neighboring semiconductor pillars being a short distance, d_s, and a distance from the central pillar to four of the six neighboring semiconductor pillars being a long distance, d_l;

with d_l being greater than d_s;

the distance d_s being along rows that extend along a first direction;

the distance d_l being along columns that extend along a second direction which intersects the first direction;

a plurality of data lines extending across the semiconductor pillars;

the data lines extending along a third direction which is offset from the first direction by less than 90 degrees, and which is substantially orthogonal to the second direction; and

wherein each of the semiconductor pillars in a respective one of the repeating pillar patterns is encompassed by a single drain-side select gate (SGD).

17. The apparatus of claim 16 wherein said each of the semiconductor pillars in a respective one of the repeating pillar patterns being encompassed by a single drain-side select gate (SGD) comprises each of the semiconductor pillars in the respective one of the repeating pillar patterns being at least partially surrounded by the single SGD, and wherein activation of the single SGD electrically couples the 7 different semiconductor pillars to 7 different data lines.

18. The apparatus of claim 17 wherein the drain-side select gate (SGD) defines a tile, and wherein there at least three pages within said tile.

19. The apparatus of claim 16 wherein d_l is at least about 1.1 times d_s.

20. The apparatus of claim 16 wherein d_l is at least about 1.3 times d_s.

21. The apparatus of claim 16 wherein d_l is at least about 1.5 times d_s.