Metal cap protection layer for gate and contact metallization

• US 9,722,038 B2
• Filed: 09/11/2015
• Issued: 08/01/2017
• Est. Priority Date: 09/11/2015
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Van Der Straten, Oscar, Reznicek, Alexander, Yang, Chih-Chao, Adusumilli, Praneet, Jagannathan, Hemanth
• Primary Examiner(s): TAYLOR, EARL N
• Application Number:
  US14/852,459
• Publication Number:
  US 20170077256A1
• Time in Patent Office: 690 Days
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53209 based on metals, e.g. alloys, metal silicides H01L23/53285 takes precedence
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A CMOS fabrication process provides metal gates and contact metallization protected by metal cap layers resistant to reagents employed in downstream processing. Cobalt gates and contact metallization are accordingly feasible in CMOS processing requiring downstream wet cleans and etch processes that would otherwise compromise or destroy them. Low resistivity metal cap materials can be employed.

Claims

1. A method comprising:

forming a sacrificial gate on a semiconductor substrate;

forming spacers on sidewalls of the sacrificial gate, the spacers having top surfaces;

removing the sacrificial gate, thereby forming a trench bounded by the spacers;

forming a gate dielectric layer within the trench;

forming a first barrier layer on the gate dielectric layer;

forming a cobalt gate on the first barrier layer;

forming a first metal cap layer sealing the cobalt gate, the first metal cap layer being entirely within the trench and entirely beneath the top surfaces of the spacers, the first metal cap layer being less chemically reactive than the cobalt gate;

forming a dielectric cap within the trench and on the first metal cap layer; and

forming an interconnect layer on the substrate by;

forming a dielectric layer on the substrate;

forming pathways within the dielectric layer;

forming a second barrier layer lining the pathways;

forming a cobalt layer within the pathways and on the second barrier layer, and

forming a second metal cap layer directly contacting and sealing the cobalt layer, the second metal cap layer being less chemically reactive than the cobalt layer.

2. The method of claim 1, wherein the step of forming the first metal cap layer further includes causing a self-aligned deposition of one or more metal layers for forming the first metal cap layer on the substrate and within the trench and recessing the one or more metal layers within the trench.

3. The method of claim 2, further comprising the step of planarizing the one or more metal layers for forming the first metal cap layer down to the spacers.

4. The method of claim 3, wherein the step of forming the interconnect layer further includes:

recessing the cobalt layer within the pathways;

causing a self-aligned deposition of one or more metal layers for forming the second metal cap layer, and

planarizing the one or more metal layers for forming the second metal cap layer such that the second metal cap layer and the dielectric layer have coplanar top surfaces.

5. The method of claim 4, wherein the first barrier layer comprises titanium nitride having a thickness of twenty nanometers or less.

6. The method of claim 5, wherein the second barrier layer comprises titanium nitride having a thickness of twenty nanometers or less.

7. The method of claim 1, wherein the first metal cap layer comprises ruthenium (Ru), rhodium (Rh), osmium (Os), iridium (Ir), molybdenum (Mo) or alloys thereof or tungsten (W) and has a thickness of three to fifteen nanometers.

8. The method of claim 1, wherein the step of forming a first metal cap layer further includes causing the selective deposition of one or more metal layers for forming the first metal cap layer on an exposed surface of the cobalt gate.

9. The method of claim 1, wherein the first metal cap layer is selected from the group consisting of ruthenium (Ru), rhodium (Rh), osmium (Os), iridium (Ir), molybdenum (Mo) and alloys thereof.

10. The method of claim 1, wherein the first barrier layer comprises titanium nitride having a thickness of five nanometers or less.

11. The method of claim 1, wherein:

the first metal cap layer is less chemically reactive to hydrofluoric acid than the cobalt gate; and

the second metal cap layer is less chemically reactive to hydrofluoric acid than the cobalt layer.

19. The method of claim 1, wherein:

the first metal cap layer is less chemically reactive than the cobalt gate during downstream CMOS processing; and

the second metal cap layer is less chemically reactive to hydrofluoric acid than the cobalt layer during downstream CMOS processing.

20. The method of claim 1, wherein:

the first metal cap layer is less chemically reactive than the cobalt gate during at least one of an etch process and wet clean; and

the second metal cap layer is less chemically reactive to hydrofluoric acid than the second cobalt layer during at least one of the etch process and wet clean.

12. A semiconductor structure comprising:

a semiconductor substrate;

a plurality of gate structures on the substrate, each gate structure including;

a pair of spacers defining a trench, the spacers including top surfaces,

a cobalt gate within the trench,

a gate dielectric layer between the semiconductor substrate and the cobalt gate,

a barrier layer between the gate dielectric layer and the cobalt gate,

a first metal cap layer sealing the cobalt gate, the first metal cap layer being positioned entirely beneath the top surfaces of the spacers and being less chemically reactive than the cobalt gate, and

a dielectric cap within the trench and on the first metal cap layer;

a dielectric layer on the substrate; and

a plurality of contact structures within the dielectric layer, each of the contact structures including;

a pathway within the dielectric layer,

a second barrier layer lining the pathway,

a cobalt layer directly contacting the second barrier layer and recessed within the pathway, and

a second metal cap layer directly contacting and sealing the cobalt layer, the second metal cap layer being less chemically reactive than the cobalt layer.

13. The semiconductor structure of claim 12, wherein the first metal cap layer comprises ruthenium (Ru), rhodium (Rh), osmium (Os), iridium (Ir), molybdenum (Mo) or alloys thereof or tungsten (W).

14. The semiconductor structure of claim 12, wherein the second metal cap layer comprises ruthenium (Ru), rhodium (Rh), osmium (Os), iridium (Ir), molybdenum (Mo) or alloys thereof or tungsten (W).

15. The semiconductor structure of claim 12, wherein:

the first metal cap layer is less chemically reactive to hydrofluoric acid than the cobalt gate; and

the second metal cap layer is less chemically reactive to hydrofluoric acid than the cobalt layer.

16. The semiconductor structure of claim 12, wherein the second metal cap layer and the dielectric layer have coplanar surfaces.

17. The semiconductor structure of claim 12, wherein the dielectric cap is entirely within the trench.

18. The semiconductor structure of claim 12, wherein the first metal cap layer includes a platinum group metal.