Semiconductor device and manufacturing method thereof

• US 9,722,055 B2
• Filed: 08/10/2016
• Issued: 08/01/2017
• Est. Priority Date: 11/07/2013
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Hanaoka, Kazuya, Kusumoto, Naoto
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US15/233,034
• Publication Number:
  US 20160351694A1
• Time in Patent Office: 356 Days
• Field of Search: 438 85, 438 86, 438104, 438149, 257 43, 257 57, 257 66, 257 67
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/2206 Amorphous materials
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 39/32 Organic image sensors

Abstract

A semiconductor device with a structure in which an increase in the number of oxygen vacancies in an oxide semiconductor layer can be suppressed and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an oxide insulating layer; intermediate layers apart from each other over the oxide insulating layer; a source electrode layer and a drain electrode layer over the intermediate layers; an oxide semiconductor layer that is electrically connected to the source electrode layer and the drain electrode layer and is in contact with the oxide insulating layer; a gate insulating film over the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and a gate electrode layer that is over the gate insulating film and overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide insulating layer over a substrate;

forming a first intermediate layer and a second intermediate layer over the oxide insulating layer;

forming a source electrode layer over the first intermediate layer;

forming a drain electrode layer over the second intermediate layer;

forming an oxide semiconductor layer over the source electrode layer and the drain electrode layer;

forming a gate insulating film over the oxide semiconductor layer; and

forming a gate electrode layer over the gate insulating film,

wherein the first intermediate layer and the source electrode layer are stacked with each other, and

wherein the second intermediate layer and the drain electrode layer are stacked with each other.

2. The method for manufacturing a semiconductor device according to claim 1,

wherein the oxide semiconductor layer comprises an In—

M—

Zn oxide, and

wherein M is at least one of Al, Ti, Ga, Y, Zr, Sn, La, Ce, Nd and Hf.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor layer includes crystals with c-axis alignment in a direction perpendicular to a surface of the oxide semiconductor layer.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor layer is stacked layers including a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer in this order from the oxide insulating layer side.

5. The method for manufacturing a semiconductor device according to claim 1, wherein each of the first intermediate layer and the second intermediate layer is a single layer or stacked layers comprising at least one material selected from the group consisting of aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia, titanium nitride, tantalum nitride, gold, platinum, palladium, and ruthenium.

6. The method for manufacturing a semiconductor device according to claim 4,

wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer each include an In—

M—

Zn oxide,

wherein M is at least one of Al, Ti, Ga, Y, Zr, Sn, La, Ce, Nd and Hf, and

wherein an atomic ratio of M to In in each of the first oxide semiconductor layer and the third oxide semiconductor layer is larger than an atomic ratio of M to In in the second oxide semiconductor layer.

7. The method for manufacturing a semiconductor device according to claim 1, wherein shapes of top surfaces of the gate electrode layer and the oxide semiconductor layer are formed so as to be substantially the same as each other.

8. The method for manufacturing a semiconductor device according to claim 4, wherein shapes of top surfaces of the gate electrode layer and the third oxide semiconductor layer are formed so as to be substantially the same as each other.