Logic circuit and semiconductor device

• US 9,722,086 B2
• Filed: 02/08/2013
• Issued: 08/01/2017
• Est. Priority Date: 10/30/2009
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Shionoiri, Yutaka, Kobayashi, Hidetomo
• Primary Examiner(s): STARK, JARRETT J
• Application Number:
  US13/762,430
• Publication Number:
  US 20130147518A1
• Time in Patent Office: 1,635 Days
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/096 Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10¹⁹ (atoms/cm³) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

Claims

1. A semiconductor device comprising:

a logic circuit configured to perform clock gating, the logic circuit comprising a first transistor and a second transistor, the first transistor and the second transistor electrically connected to each other,

wherein the first transistor comprises a silicon region in which a channel of the first transistor is formed, and

wherein the second transistor comprises an oxide semiconductor layer in which a channel of the second transistor is formed.

2. The semiconductor device according to claim 1, wherein the logic circuit comprises a flip-flop and a circuit selected from a AND gate, a NOR gate, and a latch.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, zinc, and one or more metal elements selected from gallium, aluminum, and tin.

4. The semiconductor device according to claim 1,

wherein a carrier density of the oxide semiconductor layer is 5×

10¹²/cm³ or lower,

wherein an off-current per unit channel width of the second transistor is 1×

10<sup>−

17</sup> A/micron or lower when a voltage of 1 V is applied between a source and a drain of the second transistor,

wherein the oxide semiconductor layer comprises crystals of an oxide semiconductor including indium, and

wherein the crystals are aligned so that c-axis of the crystals are in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

5. The semiconductor device according to claim 4, wherein a size of the crystals is 20 nm or less.

6. A semiconductor device comprising:

a first transistor comprises a silicon region in which a channel of the first transistor is formed;

a gate electrode layer over the first transistor;

a gate insulating layer adjacent to the gate electrode layer;

an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween;

a source electrode layer and a drain electrode layer in electrical contact with the oxide semiconductor layer; and

an oxide insulating layer in contact with the oxide semiconductor layer, the oxide semiconductor layer being located between the gate insulating layer and the oxide insulating layer,

wherein a channel is formed in the oxide semiconductor layer,

wherein the energy gap of the oxide semiconductor is higher than 2 eV, and

wherein one of the source electrode layer and the drain electrode layer is in electrical contact with the first transistor.

7. The semiconductor device according to claim 6, wherein the oxide semiconductor layer is provided over the gate electrode layer.

8. The semiconductor device according to claim 6, wherein the oxide semiconductor layer comprises indium, zinc, and one or more metal elements selected from gallium, aluminum, and tin.

9. The semiconductor device according to claim 6,

wherein a carrier density of the oxide semiconductor layer is 5×

10¹²/cm³ or lower,

wherein an off-current per unit width of the channel is 1×

10<sup>−

17</sup> A/micron or lower when a voltage of 1 V is applied between the source electrode layer and the drain electrode layer,

wherein the oxide semiconductor layer comprises crystals of an oxide semiconductor including indium, and

wherein the crystals are aligned so that c-axis of the crystals are in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

10. The semiconductor device according to claim 9, wherein a size of the crystals is 20 nm or less.

11. A semiconductor device comprising:

a first transistor comprises a silicon region in which a channel of the first transistor is formed;

a gate electrode layer over the first transistor;

a gate insulating layer adjacent to the gate electrode layer;

an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween;

a source electrode layer and a drain electrode layer in electrical contact with the oxide semiconductor layer; and

an oxide insulating layer in contact with the oxide semiconductor layer, the oxide semiconductor layer being located between the gate insulating layer and the oxide insulating layer,

wherein a channel is formed in the oxide semiconductor layer,

wherein a concentration of hydrogen in the oxide semiconductor layer is 5×

10¹⁸ atoms/cm³ or lower, and

wherein one of the source electrode layer and the drain electrode layer is in electrical contact with the first transistor.

12. The semiconductor device according to claim 11, wherein the oxide semiconductor layer is provided over the gate electrode layer.

13. The semiconductor device according to claim 11, wherein the oxide semiconductor layer comprises indium, zinc, and one or more metal elements selected from gallium, aluminum, and tin.

14. The semiconductor device according to claim 11,

wherein a carrier density of the oxide semiconductor layer is 5×

10¹²/cm³ or lower,

wherein an off-current per unit width of the channel is 1×

10<sup>−

17</sup> A/micron or lower when a voltage of 1 V is applied between the source electrode layer and the drain electrode layer,

wherein the oxide semiconductor layer comprises crystals of an oxide semiconductor including indium, and

wherein the crystals are aligned so that c-axis of the crystals are in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

15. The semiconductor device according to claim 14, wherein a size of the crystals is 20 nm or less.

16. A semiconductor device comprising:

a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer, the first transistor and the second transistor electrically connected to each other,

wherein the first transistor comprises a silicon region in which a channel of the first transistor is formed, and

wherein the second transistor comprises;

a gate electrode layer;

a gate insulating layer adjacent to the gate electrode layer;

an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween;

a source electrode layer and a drain electrode layer in electrical contact with the oxide semiconductor layer; and

an oxide insulating layer in contact with the oxide semiconductor layer, the oxide semiconductor layer being located between the gate insulating layer and the oxide insulating layer,

wherein a channel is formed in the oxide semiconductor layer, and

wherein one of the source electrode layer and the drain electrode layer is in electrical contact with the first transistor.

17. The semiconductor device according to claim 16, wherein the oxide semiconductor layer is provided over the gate electrode layer.

18. The semiconductor device according to claim 16, wherein the oxide semiconductor layer comprises indium, zinc, and one or more metal elements selected from gallium, aluminum, and tin.

19. The semiconductor device according to claim 16, wherein the first transistor is provided on a substrate comprising a semiconductor material.

20. The semiconductor device according to claim 16,

wherein a carrier density of the oxide semiconductor layer is 5×

10¹²/cm³ or lower,

wherein an off-current per unit width of the channel is 1×

10<sup>−

17</sup> A/micron or lower when a voltage of 1 V is applied between the source electrode layer and the drain electrode layer,

wherein the oxide semiconductor layer comprises crystals of an oxide semiconductor including indium, and

wherein the crystals are aligned so that c-axis of the crystals are in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

21. The semiconductor device according to claim 20, wherein a size of the crystals is 20 nm or less.

22. A semiconductor device comprising:

a first transistor comprises a silicon region in which a channel of the first transistor is formed;

a gate electrode layer over the first transistor;

a gate insulating layer adjacent to the gate electrode layer;

an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween;

a source electrode layer and a drain electrode layer in electrical contact with the oxide semiconductor layer; and

an oxide insulating layer in contact with the oxide semiconductor layer, the oxide semiconductor layer being located between the gate insulating layer and the oxide insulating layer,

wherein the oxide semiconductor layer comprises a first region and a second region,

wherein a channel is formed in the first region,

wherein the energy gap of the oxide semiconductor is higher than 2 eV, and

wherein one of the source electrode layer and the drain electrode layer is in electrical contact with the first transistor.

23. The semiconductor device according to claim 22, wherein the oxide semiconductor layer is provided over the gate electrode layer.

24. The semiconductor device according to claim 22, wherein the oxide semiconductor layer comprises indium, zinc, and one or more metal elements selected from gallium, aluminum, and tin.

25. The semiconductor device according to claim 22, wherein the second region comprises microcrystals.

26. The semiconductor device according to claim 25, wherein a size of the microcrystals is 4 nm or less.

27. The semiconductor device according to claim 22,

wherein a carrier density of the oxide semiconductor layer is 5×

10¹²/cm³ or lower,

wherein an off-current per unit width of the channel is 1×

10<sup>−

17</sup> A/micron or lower when a voltage of 1 V is applied between the source electrode layer and the drain electrode layer,

wherein the oxide semiconductor layer comprises crystals of an oxide semiconductor including indium, and

wherein the crystals are aligned so that c-axis of the crystals are in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

28. The semiconductor device according to claim 27, wherein a size of the crystals is 20 nm or less.

29. A semiconductor device comprising:

a first transistor comprises a silicon region in which a channel of the first transistor is formed;

a gate electrode layer over the first transistor;

a gate insulating layer adjacent to the gate electrode layer;

an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween;

a source electrode layer and a drain electrode layer in electrical contact with the oxide semiconductor layer; and

an oxide insulating layer in contact with the oxide semiconductor layer, the oxide semiconductor layer being located between the gate insulating layer and the oxide insulating layer,

wherein the oxide semiconductor layer comprises a first region and a second region,

wherein a channel is formed in the first region,

wherein a concentration of hydrogen in the oxide semiconductor layer is 5×

10¹⁸ atoms/cm³ or lower, and

wherein one of the source electrode layer and the drain electrode layer is in electrical contact with the first transistor.

30. The semiconductor device according to claim 29, wherein the oxide semiconductor layer is provided over the gate electrode layer.

31. The semiconductor device according to claim 29, wherein the oxide semiconductor layer comprises indium, zinc, and one or more metal elements selected from gallium, aluminum, and tin.

32. The semiconductor device according to claim 29, wherein the second region comprises microcrystals.

33. The semiconductor device according to claim 32, wherein a size of the microcrystals is 4 nm or less.

34. The semiconductor device according to claim 29,

wherein a carrier density of the oxide semiconductor layer is 5×

10¹²/cm³ or lower,

wherein an off-current per unit width of the channel is 1×

10<sup>−

17</sup> A/micron or lower when a voltage of 1 V is applied between the source electrode layer and the drain electrode layer,

wherein the oxide semiconductor layer comprises crystals of an oxide semiconductor including indium, and

wherein the crystals are aligned so that c-axis of the crystals are in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

35. The semiconductor device according to claim 34, wherein a size of the crystals is 20 nm or less.

36. A semiconductor device comprising:

a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer, the first transistor and the second transistor electrically connected to each other,

wherein the first transistor comprises a silicon region in which a channel of the first transistor is formed,

wherein the second transistor comprises;

a gate electrode layer;

a gate insulating layer adjacent to the gate electrode layer;

an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween;

a source electrode layer and a drain electrode layer in electrical contact with the oxide semiconductor layer; and

an oxide insulating layer in contact with the oxide semiconductor layer, the oxide semiconductor layer being located between the gate insulating layer and the oxide insulating layer,

wherein the oxide semiconductor layer comprises a first region and a second region, and

wherein a channel is formed in the first region.

37. The semiconductor device according to claim 36, wherein the oxide semiconductor layer is provided over the gate electrode layer.

38. The semiconductor device according to claim 36, wherein the oxide semiconductor layer comprises indium, zinc, and one or more elements selected from gallium, aluminum and tin.

39. The semiconductor device according to claim 36, wherein the first transistor is provided on a substrate comprising a semiconductor material.

40. The semiconductor device according to claim 36, wherein the second region comprises microcrystals.

41. The semiconductor device according to claim 40, wherein a size of the microcrystals is 4 nm or less.

42. The semiconductor device according to claim 36,

wherein a carrier density of the oxide semiconductor layer is 5×

10¹²/cm³ or lower,

wherein an off-current per unit width of the channel is 1×

10<sup>−

17</sup> A/micron or lower when a voltage of 1 V is applied between the source electrode layer and the drain electrode layer,

wherein the oxide semiconductor layer comprises crystals of an oxide semiconductor including indium, and

wherein the crystals are aligned so that c-axis of the crystals are in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

43. The semiconductor device according to claim 42, wherein a size of the crystals is 20 nm or less.