Oxide semiconductor transistor and manufacturing method thereof

• US 9,722,093 B1
• Filed: 09/01/2016
• Issued: 08/01/2017
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Xing, Su, Ko, Chien-Yu, Wang, Jen-Yu, Huang, Cheng-Tung, Wang, Hsueh-Wen, Tung, Yu-Cheng, Lin, Yu-Ming
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US15/253,896
• Time in Patent Office: 334 Days
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/516 with at least one ferroelectric layer
• CPC Class Codes: H01L 29/6684 with a ferroelectric gate insulator
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 51/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors

Abstract

An oxide semiconductor transistor includes an oxide semiconductor channel layer, a metal gate, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The metal gate is disposed on the oxide semiconductor channel layer. The gate insulation layer is disposed between the metal gate and the oxide semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the metal gate. The ferroelectric material layer is disposed between the internal electrode and the metal gate. The ferroelectric material layer in the oxide semiconductor transistor of the present invention is used to enhance the electrical characteristics of the oxide semiconductor transistor.

Claims

1. An oxide semiconductor transistor, comprising:

an oxide semiconductor channel layer;

a metal gate disposed on the oxide semiconductor channel layer;

a gate insulation layer disposed between the metal gate and the oxide semiconductor channel layer;

an internal electrode disposed between the gate insulation layer and the metal gate;

a ferroelectric material layer disposed between the internal electrode and the metal gate; and

a spacer disposed on the oxide semiconductor channel layer, wherein a trench surrounded by the spacer is formed above the oxide semiconductor channel layer, the ferroelectric material layer is disposed in the trench, and the metal gate is disposed outside the trench.

2. The oxide semiconductor transistor of claim 1, wherein a thickness of the ferroelectric material layer is larger than a thickness of the gate insulation layer.

3. The oxide semiconductor transistor of claim 1, wherein the ferroelectric material layer comprises a perovskite oxide material.

4. The oxide semiconductor transistor of claim 1, wherein the oxide semiconductor channel layer includes indium gallium zinc oxide (IGZO).

5. The oxide semiconductor transistor of claim 1, wherein the gate insulation layer is disposed in the trench, and the gate insulation layer comprises a U-shaped structure surrounding the ferroelectric material layer in the trench.

6. The oxide semiconductor transistor of claim 1, wherein the internal electrode is disposed in the trench, and the internal electrode comprises a U-shaped structure surrounding the ferroelectric material layer in the trench.

7. A manufacturing method of an oxide semiconductor transistor, comprising:

forming a gate insulation layer on an oxide semiconductor channel layer;

forming an internal electrode on the gate insulation layer;

forming a ferroelectric material layer on the internal electrode;

forming a metal gate on the ferroelectric material layer, wherein at least a part of the ferroelectric material layer is disposed between the metal gate and the internal electrode; and

forming a spacer on the oxide semiconductor channel layer before the step of forming the ferroelectric material layer, wherein a trench surrounded by the spacer is formed above the oxide semiconductor channel layer, and the metal gate is formed outside the trench.

8. The manufacturing method of the oxide semiconductor transistor of claim 7, wherein the step of forming the trench comprises:

forming a dummy gate on the oxide semiconductor channel layer before the step of forming the spacer, wherein the spacer is formed on a side wall of the dummy gate; and

removing the dummy gate for forming the trench surrounded by the spacer.

9. The manufacturing method of the oxide semiconductor transistor of claim 7, wherein the ferroelectric material layer is formed after the step of forming the trench, and the ferroelectric material layer is formed in the trench.

10. The manufacturing method of the oxide semiconductor transistor of claim 9, wherein the internal electrode is formed after the step of forming the trench, and the internal electrode is formed in the trench.

11. The manufacturing method of the oxide semiconductor transistor of claim 10, wherein the internal electrode comprises a U-shaped structure surrounding the ferroelectric material layer in the trench.

12. The manufacturing method of the oxide semiconductor transistor of claim 10, wherein the gate insulation layer is formed after the step of forming the trench, and the gate insulation layer is formed in the trench.

13. The manufacturing method of the oxide semiconductor transistor of claim 12, wherein the gate insulation layer comprises a U-shaped structure surrounding the internal electrode in the trench.