Current-mode logic circuit having a wide operating range
First Claim
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1. A current-mode logic (CML) circuit, comprising:
- a differential transistor pair having a differential input port configured to receive a differential input voltage, a bias port configured for coupling to a current source, and a differential output port distinct from the differential input port; and
a load circuit coupled to the differential output port, the load circuit comprising;
an active inductive load;
a cross-coupled transistor pair having sources directly coupled to a supply voltage; and
a switch comprising a first pair of transistors coupled between drains of the cross-coupled transistor pair and drains of the differential transistor pair, a transistor width of the first pair of transistors of the switch being smaller than a transistor width of the cross-coupled transistor pair.
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Abstract
In one example, a current-mode logic (CML) circuit includes a differential transistor pair having a differential input port configured to receive a differential input voltage, a bias port configured for coupling to a current source, and a differential output port. The CML circuit further includes a load circuit coupled to the differential output port. The load circuit includes an active inductive load, a cross-coupled transistor pair, and a switch coupled between the cross-coupled transistor pair and the differential output.
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Citations
18 Claims
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1. A current-mode logic (CML) circuit, comprising:
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a differential transistor pair having a differential input port configured to receive a differential input voltage, a bias port configured for coupling to a current source, and a differential output port distinct from the differential input port; and a load circuit coupled to the differential output port, the load circuit comprising; an active inductive load; a cross-coupled transistor pair having sources directly coupled to a supply voltage; and a switch comprising a first pair of transistors coupled between drains of the cross-coupled transistor pair and drains of the differential transistor pair, a transistor width of the first pair of transistors of the switch being smaller than a transistor width of the cross-coupled transistor pair. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A current-mode logic (CML) circuit, comprising:
a plurality of CML cells coupled to perform a logic operation, each of the CML cells comprising; a differential transistor pair having a differential input port configured to receive a differential input voltage, a bias port configured for coupling to a current source, and a differential output port distinct from the differential input port; and a load circuit coupled to the differential output port, the load circuit comprising; an active inductive load; a cross-coupled transistor pair having sources directly coupled to a supply voltage; and a switch comprising a first pair of transistors coupled between drains of the cross-coupled transistor pair and drains of the differential transistor pair, a transistor width of the first pair of transistors of the switch being smaller than a transistor width of the cross-coupled transistor pair. - View Dependent Claims (10, 11, 12, 13)
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14. A method of operating a current-mode logic (CML) circuit having a differential transistor pair coupled to a load circuit configured for inductive broadbanding, the method comprising:
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coupling a differential input signal to a differential input port of a differential transistor pair, the differential transistor pair having a differential output port distinct from the differential input port; controlling a switch comprising a first pair of transistors to couple a cross-coupled transistor pair of the load circuit to the differential output port of the differential transistor pair, sources of the cross-coupled transistor pair being directly coupled to a supply voltage, a transistor width of the first pair of transistors of the switch being smaller than a transistor width of the cross-coupled transistor pair; and receiving a differential output signal from the differential output port of the differential transistor pair. - View Dependent Claims (15, 16, 17, 18)
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Specification