Integrated level shifter

• US 9,722,609 B2
• Filed: 02/13/2017
• Issued: 08/01/2017
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Navitas Semiconductor, Inc.
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel Marvin, Sharma, Santosh, Zhang, Ju
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US15/431,632
• Publication Number:
  US 20170155391A1
• Time in Patent Office: 169 Days
• Field of Search: None
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02M 1/0048 : Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 1/088 : for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/155 : using semiconductor devices only
• CPC Class Codes: H02M 3/157 : with digital control
• CPC Class Codes: H02M 3/1584 : with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1588 : comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/102 : in field-effect transistor switches
• CPC Class Codes: H03K 19/018507 : Interface arrangements
• CPC Class Codes: H03K 3/012 : Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356017 : using additional transistors in the input circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: Y02B 40/00 : Technologies aiming at improving the efficiency of home appliances, e.g. induction cooking or efficient technologies for refrigerators, freezers or dish washers
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Claims

1. A level shift circuit comprising:

a GaN-based level shift transistor, comprising;

a gate connected to a gate terminal,

a drain connected to a drain terminal, and

a source connected to a source terminal,

wherein the level shift transistor is configured to receive an input referenced to a ground at the gate terminal and to generate an output at the drain terminal, wherein the output is referenced to a floating voltage.

2. The level shift circuit of claim 1, further comprising an electronically conductive element between the source terminal and a ground.

3. The level shift circuit of claim 1, further comprising:

a first conductive element connected between the drain terminal and a floating power supply; and

a first pull up transistor connected between the drain terminal and the floating power supply.

4. The level shift circuit of claim 1, wherein the level shift transistor is configured to receive a pulsed input signal, and wherein a duration of one or more pulses of the pulsed input signal is less than 500 nanoseconds.

5. The level shift circuit of claim 1, wherein the level shift transistor is configured to receive a pulsed input signal, and wherein a duration of one or more pulses of the pulsed input signal is less than 200 nanoseconds.

6. The level shift circuit of claim 1, wherein the level shift transistor is configured to receive a pulsed input signal, and wherein a duration of one or more pulses of the pulsed input signal is less than 100 nanoseconds.

7. The level shift circuit of claim 1, wherein the level shift transistor is configured to receive a pulsed input signal, and wherein a duration of one or more pulses of the pulsed input signal is less than 75 nanoseconds.

8. The level shift circuit of claim 1, wherein a channel width of the level shift transistor is less than 100 microns.

9. The level shift circuit of claim 1, wherein a channel width of the level shift transistor is less than 50 microns.

10. The level shift circuit of claim 1, wherein a channel width of the level shift transistor is less than 10 microns.

11. The level shift circuit of claim 1, wherein a channel width of the level shift transistor is less than 5 microns.

12. The level shift circuit of claim 1, wherein the level shift transistor is configured to conduct not more than 2 milliamps.

13. The level shift circuit of claim 1, wherein the level shift transistor is rated for 650V.

14. The level shift circuit of claim 1, wherein the level shift transistor has less than 25 picocoulombs of output charge (Qoss).

15. The level shift circuit of claim 1, wherein the level shift transistor includes a source ohmic contact area connected to a source terminal, wherein the source terminal is connected to a metal pad that is adjacent to the source terminal, and wherein the metal pad has an area greater than 100 times area of the source ohmic contact.

16. The level shift circuit of claim 1, wherein the level shift transistor includes a drain ohmic contact area connected to a drain terminal, and the drain terminal is connected to a metal pad that is that is adjacent to the source terminal, and wherein the metal pad has an area greater than 100 times area of the drain ohmic contact.

17. The level shift circuit of claim 16, further comprising a conductive shield underneath the metal pad.

18. The level shift circuit of claim 17, wherein the conductive shield is referenced to the floating supply.

19. The level shift circuit of claim 17, wherein the conductive shield is referenced to ground.

20. The level shift circuit of claim 1, wherein the level shift transistor comprises a source area and a drain area and the source area does not encircle the drain area.