Circuit arrangement for and a method of enabling a partial reconfiguration of a circuit implemented in an integrated circuit device

• US 9,722,613 B1
• Filed: 09/28/2015
• Issued: 08/01/2017
• Est. Priority Date: 09/28/2015
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lu, Weiguang, Schultz, David P., Kolze, Paige A.
• Primary Examiner(s): Taningco, Alexander H
• Assistant Examiner(s): Bahr, Kurtis R
• Application Number:
  US14/867,461
• Time in Patent Office: 673 Days
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration

Abstract

A circuit arrangement for enabling a partial reconfiguration of a circuit implemented in an integrated circuit device is described. The circuit arrangement comprises a plurality of circuit blocks, wherein each circuit block is configurable to implement a predetermined function and comprises a control circuit configured to receive a global enable signal and a plurality of global reconfiguration signals; and a routing network coupled to the plurality of circuit blocks for routing the global enable signal and the plurality of global reconfiguration signals to each circuit block of the plurality of circuit blocks; wherein each circuit block of the plurality of circuit blocks is configured to independently receive a local enable signal enabling a partial reconfiguration of the circuit in response to the plurality of global reconfiguration signals.

Claims

1. A circuit arrangement for enabling a partial reconfiguration of a circuit implemented in an integrated circuit device, the circuit arrangement comprising:

a plurality of configurable logic blocks, wherein each configurable logic blocks has a lookup table and is configurable to implement a predetermined function and comprises a control circuit configured to receive a global enable signal and a plurality of global reconfiguration signals; and

a routing network coupled to the plurality of configurable logic blocks for routing the global enable signal and the plurality of global reconfiguration signals to each configurable logic block of the plurality of configurable logic blocks;

wherein each configurable logic block of the plurality of configurable logic blocks is configured to independently receive a local enable signal enabling a partial reconfiguration of the plurality of configurable logic blocks in response to the plurality of global reconfiguration signals; and

wherein the control circuit generates a reconfiguration enable signal in response to either the global enable signal or the local enable signal, and the reconfiguration enable signal generated in response to the local enable signal enables the partial reconfiguration of the plurality of configurable logic blocks using local configuration signals based upon the global reconfiguration signals.

2. The circuit arrangement of claim 1, wherein the global enable signal enables a reconfiguration of each of the configurable logic blocks of the plurality of configurable logic blocks.

3. The circuit arrangement of claim 1, wherein the global enable signal overrides the local enable signal.

4. The circuit arrangement of claim 3, wherein each configurable logic block of the plurality of configurable logic blocks is reconfigured in response to the global enable signal and a plurality of local reconfiguration signals.

5. The circuit arrangement of claim 1, wherein the plurality of global reconfiguration signals comprises a global interconnect control signal, a global write enable signal, and a global reset signal.

6. The circuit arrangement of claim 1, further comprising digital signal processor blocks, blocks of random access memory, input/output blocks, bus controller blocks, Ethernet MAC blocks, and Interlaken blocks.

7. The circuit arrangement of claim 1, wherein each configurable logic block of the plurality of configurable logic blocks has a register configured to receive the local reconfiguration signals.

8. The circuit arrangement of claim 1, wherein the control circuit further comprises a plurality of gating circuits configured to receive the plurality of global reconfiguration signals and generate the local reconfiguration signals.

9. The circuit arrangement of claim 8, wherein the plurality of gating circuits comprises at least one gating circuit from a group consisting of a first gating circuit configured to receive a global interconnect control signal and generate a local interconnect control signal, a second gating circuit configured to receive a global write enable signal and generate a local write enable signal, and a third gating circuit configured to receive a global restore signal and generate a local restore signal.

10. A method of enabling a partial reconfiguration of a circuit implemented in an integrated circuit device, the method comprising:

implementing a plurality of configurable logic blocks in an integrated circuit device, wherein each configurable logic block has a lookup table and is configurable to implement a predetermined function;

routing a global enable signal and the plurality of global reconfiguration signals to each configurable logic block of a plurality of configurable logic blocks; and

independently coupling a local enable signal to a control circuit of each configurable logic block of the plurality of configurable logic blocks, the local enable signal enabling a partial reconfiguration of the plurality of configurable logic blocks in response to the plurality of global reconfiguration signals; and

generating a reconfiguration enable signal in response to either the global enable signal or the local enable signal;

wherein the reconfiguration enable signal generated in response to the local enable signal enables the partial reconfiguration of the plurality of configurable logic blocks using local configuration signals based upon the global reconfiguration signals.

11. The method of claim 10, further comprising reconfiguring each configurable logic block of the plurality of configurable logic blocks in response to the global enable signal.

12. The method of claim 11, further comprising overriding the local enable signal received at the configurable logic block of the plurality of configurable logic blocks using the global enable signal.

13. The method of claim 12, further comprising generating a plurality of local reconfiguration signals based upon the global reconfiguration signals, and reconfiguring each configurable logic block of the plurality of configurable logic blocks in response to the global enable signal and the plurality of local reconfiguration signals.

14. The method of claim 10, wherein receiving a plurality of global reconfiguration signals comprises receiving a global interconnect control signal, a global write enable signal, and a global reset signal.

15. The method of claim 10, further comprising implementing digital signal processor blocks, blocks of random access memory, input/output blocks, bus controller blocks, Ethernet MAC blocks, and Interlaken blocks.

16. The method of claim 10, wherein each configurable logic block of the plurality of configurable logic blocks has a register configured to receive the reconfiguration signals.

17. The method of claim 10, further comprising implementing a plurality of gating circuits configured to receive the plurality of global reconfiguration signals and generate the local reconfiguration signals.

18. The method of claim 17, wherein implementing a plurality of gating circuits comprises implementing at least one gating circuit from a group consisting of a first gating circuit for receiving a global interconnect control signal and generating a local interconnect control signal, a second gating circuit for receiving a global write enable signal and generating a local write enable signal, and a third gating circuit for receiving a global restore signal and generating a local restore signal.