Circuit arrangement for and a method of enabling a partial reconfiguration of a circuit implemented in an integrated circuit device
First Claim
1. A circuit arrangement for enabling a partial reconfiguration of a circuit implemented in an integrated circuit device, the circuit arrangement comprising:
- a plurality of configurable logic blocks, wherein each configurable logic blocks has a lookup table and is configurable to implement a predetermined function and comprises a control circuit configured to receive a global enable signal and a plurality of global reconfiguration signals; and
a routing network coupled to the plurality of configurable logic blocks for routing the global enable signal and the plurality of global reconfiguration signals to each configurable logic block of the plurality of configurable logic blocks;
wherein each configurable logic block of the plurality of configurable logic blocks is configured to independently receive a local enable signal enabling a partial reconfiguration of the plurality of configurable logic blocks in response to the plurality of global reconfiguration signals; and
wherein the control circuit generates a reconfiguration enable signal in response to either the global enable signal or the local enable signal, and the reconfiguration enable signal generated in response to the local enable signal enables the partial reconfiguration of the plurality of configurable logic blocks using local configuration signals based upon the global reconfiguration signals.
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Abstract
A circuit arrangement for enabling a partial reconfiguration of a circuit implemented in an integrated circuit device is described. The circuit arrangement comprises a plurality of circuit blocks, wherein each circuit block is configurable to implement a predetermined function and comprises a control circuit configured to receive a global enable signal and a plurality of global reconfiguration signals; and a routing network coupled to the plurality of circuit blocks for routing the global enable signal and the plurality of global reconfiguration signals to each circuit block of the plurality of circuit blocks; wherein each circuit block of the plurality of circuit blocks is configured to independently receive a local enable signal enabling a partial reconfiguration of the circuit in response to the plurality of global reconfiguration signals.
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Citations
18 Claims
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1. A circuit arrangement for enabling a partial reconfiguration of a circuit implemented in an integrated circuit device, the circuit arrangement comprising:
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a plurality of configurable logic blocks, wherein each configurable logic blocks has a lookup table and is configurable to implement a predetermined function and comprises a control circuit configured to receive a global enable signal and a plurality of global reconfiguration signals; and a routing network coupled to the plurality of configurable logic blocks for routing the global enable signal and the plurality of global reconfiguration signals to each configurable logic block of the plurality of configurable logic blocks; wherein each configurable logic block of the plurality of configurable logic blocks is configured to independently receive a local enable signal enabling a partial reconfiguration of the plurality of configurable logic blocks in response to the plurality of global reconfiguration signals; and wherein the control circuit generates a reconfiguration enable signal in response to either the global enable signal or the local enable signal, and the reconfiguration enable signal generated in response to the local enable signal enables the partial reconfiguration of the plurality of configurable logic blocks using local configuration signals based upon the global reconfiguration signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of enabling a partial reconfiguration of a circuit implemented in an integrated circuit device, the method comprising:
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implementing a plurality of configurable logic blocks in an integrated circuit device, wherein each configurable logic block has a lookup table and is configurable to implement a predetermined function; routing a global enable signal and the plurality of global reconfiguration signals to each configurable logic block of a plurality of configurable logic blocks; and independently coupling a local enable signal to a control circuit of each configurable logic block of the plurality of configurable logic blocks, the local enable signal enabling a partial reconfiguration of the plurality of configurable logic blocks in response to the plurality of global reconfiguration signals; and generating a reconfiguration enable signal in response to either the global enable signal or the local enable signal; wherein the reconfiguration enable signal generated in response to the local enable signal enables the partial reconfiguration of the plurality of configurable logic blocks using local configuration signals based upon the global reconfiguration signals. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification