System and method for retaining DRAM data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem

• US 9,727,269 B2
• Filed: 12/23/2016
• Issued: 08/08/2017
• Est. Priority Date: 05/27/2014
• Status: Active Grant

• Current Assignee: FG SRC LLC (Freeman Capital Partners LP)
• Original Assignee: SRC Labs, LLC (Freeman Capital Partners LP)
• Inventors: Tewalt, Timothy J.
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US15/389,650
• Publication Number:
  US 20170102894A1
• Time in Patent Office: 228 Days
• Field of Search: 711101
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting

Abstract

A system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers such as field programmable gate arrays (FPGAs). The DRAM memory controller is utilized in concert with a data maintenance block collocated with the DRAM memory and coupled to an I2C interface of the reconfigurable device, wherein the FPGA drives the majority of the DRAM input/output (I/O) and the data maintenance block drives the self-refresh command inputs. Even though the FPGA reconfigures and the majority of the DRAM inputs are tri-stated, the data maintenance block provides stable input levels on the self-refresh command inputs.

Claims

1. A computer system comprising:

a reconfigurable processor comprising a number of processing elements, a memory subsystem query controller and a reconfigurable memory controller; and

a memory subsystem comprising a plurality of memory storage elements and an associated subsystem status information block, said reconfigurable memory controller being coupled to said memory storage elements and said memory subsystem query controller being coupled to said subsystem status information block and said reconfigurable memory controller wherein said subsystem status information block is operative to provide a current state of said memory subsystem to said reconfigurable memory controller.

2. The computer system of claim 1 wherein said reconfigurable processor comprises an FPGA.

3. The computer system of claim 1 wherein said memory storage elements comprise persistent memory.

4. The computer system of claim 3 wherein said persistent memory comprises at least one of NAND Flash, PCM, FeRAM or 3D Xpoint memory.

5. The computer system of claim 1 wherein said current state of said memory subsystem comprises at least one of a state of initialization or readiness, base and limit addresses or table lookaside buffer mapping contents of said memory subsystem.

6. The computer system of claim 1 wherein the memory subsystem query controller is collocated within the reconfigurable processor.

7. The computer system of claim 1 wherein the memory subsystem query controller is collocated within the reconfigurable memory controller.

8. The computer system of claim 1 wherein memory subsystem queries are performed by the reconfigurable processor.

9. The computer system of claim 1 wherein memory subsystem queries are performed by the reconfigurable memory controller.

10. The computer system of claim 1 wherein said current state of said memory subsystem comprises at least one of a state of pre-runtime contents, including but not limited to initialization or readiness, base and limit addresses or table lookaside buffer mapping contents of said memory subsystem.

11. The computer system of claim 1 wherein said current state of said memory subsystem comprises at least one of a state of non-runtime contents, including but not limited to environmental conditions, serial number, security keys, selftest results, power cycles, hour meter or firmware revisions of said memory subsystem.

12. The computer system of claims 1 wherein said current state of said memory subsystem comprises runtime contents, of said memory subsystem used for billing customers in a configurable cloud processing environment.

13. The computer system of claim 12 wherein said memory elements comprise a NAND Flash, and said runtime content includes excessive writes to said NAND Flash.

14. The computer system of claim 1 wherein said current state of said memory subsystem and an associated subsystem status information block includes a backup power source or persistent memory device which back up data when the subsystem is hot swapped.

15. The computer system of claim 1 wherein said current state of said memory subsystem and an associated subsystem status information block includes a backup power source or persistent memory device which back up data when the subsystem is powered down and relocated to a mobile device.

16. The computer system of claim 1 wherein said current state of said memory subsystem and an associated subsystem status information block includes an auxiliary port for direct communication with a duplicate local or remote subsystem when used in a redundant fashion.

17. The computer system of claim 1 wherein said current state of said memory subsystem and an associated subsystem status information block includes an auxiliary port for direct communication when information is transferred to a mobile device.

19. The method of claim 17 wherein said status information comprises a confirmation that said memory is initialized, and an address identifying information needed for said second task.

20. The method of claim 17 wherein said status information comprises a processor table map.

21. The method of claim 17 wherein said status information comprises an address pointer indicative of a location containing a data set produced by said first task.

22. The method of claim 21 wherein said second task can locate and use said data set produced by said first task.

18. A method of processing information in a reconfigurable computing system having a reconfigurable processor comprising a memory subsystem query controller and a reconfigurable memory controller, a memory subsystem comprising a plurality of memory storage elements and an associated subsystem status information block, the method comprising:

during processing of a first task by the reconfigurable processor, the memory controller transmitting status information to the memory subsystem and the subsystem status information block maintaining data received from the memory controller;

upon completion of the first task, the memory subsystem maintaining memory status information indicative of a memory status;

reconfiguring the reconfigurable processor to carry out a second task; and

upon reconfiguration, the reconfigurable processor querying the memory subsystem to provide memory status information, wherein the memory status information can then be used to complete the second task.