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System and method for retaining DRAM data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem

  • US 9,727,269 B2
  • Filed: 12/23/2016
  • Issued: 08/08/2017
  • Est. Priority Date: 05/27/2014
  • Status: Active Grant
First Claim
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1. A computer system comprising:

  • a reconfigurable processor comprising a number of processing elements, a memory subsystem query controller and a reconfigurable memory controller; and

    a memory subsystem comprising a plurality of memory storage elements and an associated subsystem status information block, said reconfigurable memory controller being coupled to said memory storage elements and said memory subsystem query controller being coupled to said subsystem status information block and said reconfigurable memory controller wherein said subsystem status information block is operative to provide a current state of said memory subsystem to said reconfigurable memory controller.

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