Data storage device and flash memory control method

• US 9,727,271 B2
• Filed: 02/21/2017
• Issued: 08/08/2017
• Est. Priority Date: 12/26/2013
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion)
• Inventors: Lin, Chien-Cheng, Huang, Chang-Chieh, Lee, Jie-Hao, Liang, Chia-Chi
• Primary Examiner(s): Perez-Velez, Rocio Del Mar
• Application Number:
  US15/437,543
• Publication Number:
  US 20170160942A1
• Time in Patent Office: 168 Days
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 11/1435 using file system or storage system metadata
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2029/0411 : Online error correction
• CPC Class Codes: G11C 2211/5641 : Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data storage device with flash memory and a flash memory control method are disclosed, in which the flash memory includes multi-level cells (MLCs) and single-level cells (SLCs). A microcontroller is configured to use the random access memory to cache data issued from the host before writing the data into the flash memory. The microcontroller is further configured to allocate the blocks of the flash memory to provide a first run-time write block containing multi-level cells and a second run-time write block containing single-level cells. Under control of the microcontroller, each physical page of data uploaded from the random access memory to the first run-time write block contains sequential data, and random data cached in the random access memory to form one physical page is written into the second run-time write block.

Claims

1. A data storage device, comprising:

a flash memory including multi-level cells and single-level cells, wherein the flash memory is divided into a plurality of blocks with each block comprising a plurality of physical pages; and

a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory,

wherein;

the microcontroller is configured to use the random access memory to cache data issued from the host before writing the data into the flash memory;

the microcontroller is further configured to allocate the blocks of the flash memory to provide a first run-time write block containing multi-level cells and a second run-time write block containing single-level cells;

each physical page of data uploaded from the random access memory to the first run-time write block contains sequential data;

random data cached in the random access memory to form one physical page is written into the second run-time write block; and

when determining that a first physical page of data that has been uploaded from the random access memory to the second run-time write block contains random data, the microcontroller is configured to write a second physical page of data, cached in the random access memory after the first physical page of data, into the second run-time write block, before checking whether the second physical page of data contains random or sequential data.

2. The data storage device as claimed in claim 1, wherein:

the microcontroller is configured to check data type before writing data into the first run-time write block, to ensure that each physical page of data uploaded from the random access memory to the first run-time write block contains sequential data.

3. The data storage device as claimed in claim 1, wherein:

the microcontroller is further configured to check whether the second physical page of data contains sequential data or random data to speculate about data type of a third physical page of data cached in the random access memory later than the second physical page of data.

4. The data storage device as claimed in claim 3, wherein:

when the second physical page of data contains random data, the microcontroller is configured to speculate that the third physical page of data contains random data and writes the third physical page of data into the second run-time write block.

5. The data storage device as claimed in claim 3, wherein:

when the second physical page of data contains sequential data, the microcontroller is configured to check data type of the third physical page of data prior to writing the third physical page of data into the flash memory;

when the third physical page of data is confirmed to be containing sequential data, the microcontroller is configured to write the third physical page of data into the first run-time write block; and

when the third physical page of data is confirmed to be containing random data, the microcontroller is configured to write the third physical page of data into the second run-time write block.

6. A flash memory control method, comprising:

providing a random access memory for a flash memory, wherein the flash memory includes multi-level cells and single-level cells and is divided into a plurality of blocks with each block comprising a plurality of physical pages;

using the random access memory to cache data issued from a host before writing the data into the flash memory; and

allocating the blocks of the flash memory to provide a first run-time write block containing multi-level cells and a second run-time write block containing single-level cells,

wherein;

each physical page of data uploaded from the random access memory to the first run-time write block contains sequential data;

random data cached in the random access memory to form one physical page is written into the second run-time write block; and

when determining that a first physical page of data that has been uploaded from the random access memory to the second run-time write block contains random data, a second physical page of data cached in the random access memory after the first physical page of data is written into the second run-time write block, before checking whether the second physical page of data contains random or sequential data.

7. The flash memory control method as claimed in claim 6, further comprising:

checking data type before writing data into the first run-time write block, to ensure that each physical page of data uploaded from the random access memory to the first run-time write block contains sequential data.

8. The flash memory control method as claimed in claim 6, further comprising:

checking whether the second physical page of data contains sequential data or random data to speculate about data type of a third physical page of data cached in the random access memory later than the second physical page of data.

9. The flash memory control method as claimed in claim 8, further comprising:

when the second physical page of data contains random data, speculating that the third physical page of data contains random data and writing the third physical page of data into the second run-time write block.

10. The flash memory control method as claimed in claim 8, wherein:

when the second physical page of data contains sequential data, data type of the third physical page of data is checked prior to writing the third physical page of data into the flash memory;

when the third physical page of data is confirmed to be containing sequential data, the third physical page of data is written into the first run-time write block; and

when the third physical page of data is confirmed to be containing random data, the third physical page of data is written into the second run-time write block.