Vector exception code

• US 9,727,334 B2
• Filed: 12/05/2014
• Issued: 08/08/2017
• Est. Priority Date: 01/23/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bradbury, Jonathan D., Schwarz, Eric M., Slegel, Timothy J., Gschwind, Michael K.
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US14/562,132
• Publication Number:
  US 20150143074A1
• Time in Patent Office: 977 Days
• Field of Search: None
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/323 for indirect branch instructions
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the instruction, a vector exception code is provided that indicates a position within the vector register that caused the exception. The vector exception code also includes a reason for the exception.

Claims

1. A method of facilitating exception handling, the method comprising:

determining, by a processor, that an instruction executing within a computing environment has caused an exception, the instruction to operate on a vector register comprising a plurality of elements;

obtaining, based on the exception, a vector exception code, the vector exception code including a position of an element of the plurality of elements of the vector register that caused the exception; and

outputting the vector exception code, including the position within the vector register of the element that caused the exception, in order to perform one or more actions based on the vector exception code.

2. The method of claim 1, wherein the position comprises an index within the vector register corresponding to the element that caused the exception.

3. The method of claim 1, wherein the position comprises a lowest indexed element in the vector register which caused the exception.

4. The method of claim 1, wherein the obtaining is based on the exception causing an interrupt.

5. The method of claim 1, wherein the vector exception code comprises a first portion to specify the position, and a second portion to specify a vector interrupt code.

6. The method of claim 5, wherein the position comprises a lowest indexed element in the vector register which caused the exception.

7. The method of claim 5, wherein the vector interrupt code comprises a value to indicate one of an invalid operation, division by zero, an overflow, an underflow or an inexact result.

8. The method of claim 1, further comprising determining which one or more elements of the vector register caused the exception, and obtaining, based on the determining which one or more elements caused the exception, the position to be included in the vector exception code.

9. The method of claim 8, wherein the obtaining the position comprises determining the lowest indexed element of the one or more elements that caused the exception and using an index of the lowest indexed element as the position.

10. The method of claim 1, wherein the instruction includes at least one Single Instruction, Multiple Data operation.

11. The method of claim 1, further comprising placing the vector exception code in a data exception code field of a floating point control register.

12. The method of claim 1, wherein a size of the element is specified in a field of the instruction.