Memory controller that provides addresses to host for memory location matching state tracked by memory controller

• US 9,727,454 B2
• Filed: 08/22/2014
• Issued: 08/08/2017
• Est. Priority Date: 01/28/2013
• Status: Active Grant

• Current Assignee: Radian Memory Systems, Inc.
• Original Assignee: Radian Memory Systems, Inc.
• Inventors: Kuzmin, Andrey V., Jadon, Mike, Mathews, Richard M.
• Primary Examiner(s): Birkhimer, Christopher D
• Application Number:
  US14/466,167
• Publication Number:
  US 20140365719A1
• Time in Patent Office: 1,082 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage. The disclosed techniques are especially useful for direct-attached and/or network-attached storage.

Claims

1. A memory controller integrated circuit for flash memory, the memory controller integrated circuit to store and retrieve data at locations in the flash memory responsive to host commands, the memory controller integrated circuit comprising:

storage for entries, each entry representing status of a page in the flash memory capable of storing data pursuant to the host commands, all pages capable of storing data pursuant to the host commands having a corresponding entry regardless of the values of data stored in a given one of the pages;

logic to update the entries responsive to changes in status of corresponding pages in the flash memory;

logic to receive a query from the host which seeks identification of one or more of the locations in the flash memory that satisfy at least one condition from the set of (a) data stored at the corresponding location satisfies a data age requirement, (b) data stored at the corresponding location satisfies an access frequency requirement, (c) a requisite number of physical pages at the corresponding location have been released but are in an unerased condition, or (d) all physical pages corresponding to the location have been released but are in an unerased condition;

logic to detect, responsive to the query, when the entries indicate that one or more of the locations in the flash memory satisfy the at least one condition; and

logic to, responsive to detection that the one or more locations satisfy the at least one condition, to transmit address information to the host corresponding to the one or more locations for which the at least one condition is satisfied; and

logic to receive from the host a maintenance command dependent on the address information transmitted to the host and to process the received maintenance command, wherein the maintenance command is to cause said memory controller integrated circuit to perform at least one of (i) relocation of a page within the one or more locations to a different erase block in the flash memory or (ii) erasure of an erase block corresponding to the one or more locations, and wherein the maintenance command is to specify an address of each page or erase block within the one or more locations that is to be the subject of the at least one of relocation or erasure pursuant to the maintenance command.

2. The memory controller integrated circuit of claim 1, wherein the logic to transmit the address information to the host is further to transmit to the host status information for an erase block corresponding to the address information.

3. The memory controller integrated circuit of claim 1, wherein the address information includes an address for a physical page of memory cells, and wherein the address specified by the maintenance command includes an address of at least one of the physical page or an erase block corresponding to the physical page.

4. The memory controller integrated circuit of claim 1, wherein the entries include information indicating page release status of the corresponding pages in the flash memory.

5. The memory controller integrated circuit of claim 1, wherein the memory controller integrated circuit is to receive an erase command from the host that specifies a physical address of an erase block in the flash memory, the address information sent to the host by the memory controller integrated circuit defining a location in the flash memory that is in an unerased condition, the erase command responsive to the address information.

6. The memory controller integrated circuit of claim 1, wherein the memory controller integrated circuit is programmable by the host to define in the memory controller integrated circuit a threshold associated with the at least one condition .

7. The memory controller integrated circuit of claim 1, wherein the address information comprises at least an identification of a page offset within an erase unit specified by the address information.

8. The memory controller integrated circuit of claim 1, wherein the entries include information indicating data age information for data stored in the corresponding pages in the flash memory, the data age information for each entry sufficient to identify the hot-cold status of data stored at the corresponding page relative to data stored at other pages in the flash memory.

9. The memory controller integrated circuit of claim 1, wherein the entries include information indicating access frequency for data stored in the corresponding pages in the flash memory, relative to data stored at other pages in the flash memory.

10. The memory controller integrated circuit of claim 1, wherein the logic to receive the maintenance command from the host dependent on the address information transmitted to the host and to process the received maintenance command is further to receive each of relocation commands and an erasure commands, and further includes logic to cause said memory controller integrated circuit to perform each of (i) relocation of a page within the one or more locations to a different erase block in the flash memory and (ii) erasure of an erase block corresponding to the one or more locations, depending on whether a relocation command or an erasure command is transmitted to said memory controller integrated circuit responsive to the address information transmitted to the host.