Translating an address associated with a command communicated between a system and memory circuits

• US 9,727,458 B2
• Filed: 09/14/2012
• Issued: 08/08/2017
• Est. Priority Date: 02/09/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Wang, David T., Rajan, Suresh Natarajan, Schakel, Keith R., Smith, Michael John Sebastian, Weber, Frederick Daniel
• Primary Examiner(s): Lo, Ann J
• Assistant Examiner(s): LOONAN, ERIC T
• Application Number:
  US13/620,650
• Publication Number:
  US 20130103897A1
• Time in Patent Office: 1,789 Days
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

Claims

1. An apparatus comprising:

an interface circuit electrically connected to a first number of physical dynamic random access memory (“

DRAM”

) devices via multiple data paths including a first data path and a distinct second data path, wherein each of the physical DRAM devices is an individual and independent monolithic device, the interface circuit configured to;

communicate with the first number of physical DRAM devices and a memory controller,

interface the first number of physical DRAM devices to simulate a different, second number of virtual DRAM devices as presented to the memory controller, each of the virtual DRAM devices being simulated as an individual and independent monolithic device,

simulate a first virtual DRAM device using a first physical DRAM device on the first data path and a second physical DRAM device on the distinct second data path,

use both a physical row of the first physical DRAM device and a physical row of the second physical DRAM device to simulate a virtual row of the first virtual DRAM device,

receive a row-access command from the memory controller, directed to the first virtual DRAM device, for the virtual row of the first virtual DRAM device,

based on the received row-access command, translate the received row-access command for the virtual row to a first row access command for the physical row of the first physical DRAM device and a second row access command for the physical row of the second physical DRAM device, and

issue the first row access command and the second row access command to activate the physical row of the first physical DRAM device and the physical row of the second physical DRAM device, respectively, before a subsequent column-access command is received from the memory controller to access a part of the simulated row that corresponds to the physical row of the first physical DRAM device or the physical row of the second physical DRAM device.

2. The apparatus of claim 1, wherein the virtual row has a virtual row size and each of the physical rows has a physical row size, and the virtual row size is greater than the physical row size.

3. The apparatus of claim 1, wherein the first number of physical DRAM devices are associated with first command scheduling constraints and the different, second number of virtual DRAM devices are associated with second command scheduling constraints different from the first command scheduling constraints;

and

the interface circuit is further configured to interface the first number of physical DRAM devices to the memory controller such that the first command scheduling constraints are met.

4. The apparatus of claim 3, wherein the first command scheduling constraints and the second command scheduling constraints include intra-device command scheduling constraints.

5. The apparatus of claim 4, wherein the intra-device command scheduling constraints include at least one of a column to column delay time (tCCD), a row to row activation delay time (tRRD), a four-bank activation window time (tFAW), or a write-to-read turn-around time (tWTR).

6. The apparatus of claim 3, wherein the first command scheduling constraints and the second command scheduling constraints include inter-device command scheduling constraints.

7. The apparatus of claim 6, wherein the inter-device command scheduling constraints include at least one of a rank to rank data bus turnaround time or an on die termination (ODT) control switching time.

8. The apparatus of claim 1, wherein the interface circuit is a circuit separate from the physical DRAM devices and is positioned on a dual inline memory module (DIMM) with the physical DRAM devices.

9. The apparatus of claim 1, wherein each of the first number of physical DRAM devices comprises a respective plurality of physical memory banks, and wherein each of the second number of virtual DRAM devices comprises two or more physical memory banks of at least two physical DRAM devices of the first number of physical DRAM devices.

10. A system comprising:

a first number of physical dynamic random access memory (“

DRAM”

) devices;

an interface circuit electrically connected to the first number of physical DRAM devices via multiple data paths including a first data path and a distinct second data path, wherein each of the physical DRAM devices is an individual and independent monolithic device, the interface circuit configured to;

communicate with the first number of physical DRAM devices and a memory controller,

interface the first number of physical DRAM devices to simulate a different, second number of virtual DRAM devices as presented to the memory controller, each of the virtual DRAM devices being simulated as an individual and independent monolithic device,

simulate a first virtual DRAM device using a first physical DRAM device on the first data path and a second physical DRAM device on the distinct second data path,

use both a physical row of the first physical DRAM device and a physical row of the second physical DRAM device to simulate a virtual row of the first virtual DRAM device,

receive a row-access command from the memory controller, directed to the first virtual DRAM device, for the virtual row of the first virtual DRAM device,

based on the received row-access command, translate the received row-access command for the virtual row to a first row access command for the physical row of the first physical DRAM device and a second row access command for the physical row of the second physical DRAM device, and

issue the first row access command and the second row access command to activate the physical row of the first physical DRAM device and the physical row of the second physical DRAM device, respectively, before a subsequent column-access command is received from the memory controller to access a part of the simulated row that corresponds to the physical row of the first physical DRAM device or the physical row of the second physical DRAM device.

11. The system of claim 10, wherein the virtual row has a virtual row size and each of the physical rows has a physical row size, and the virtual row size is greater than the physical row size.

12. The system of claim 10, wherein the first number of physical DRAM devices are associated with first command scheduling constraints and the different, second number of virtual DRAM devices are associated with second command scheduling constraints different from the first command scheduling constraints;

and

the interface circuit is further configured to interface the first number of physical DRAM devices to the memory controller such that the first command scheduling constraints are met.

13. The system of claim 12, wherein the first command scheduling constraints and the second command scheduling constraints include intra-device command scheduling constraints.

14. The system of claim 12, wherein the first command scheduling constraints and the second command scheduling constraints include inter-device command scheduling constraints.

15. The system of claim 10, wherein each of the first number of physical DRAM devices comprises a respective plurality of physical memory banks, and wherein each of the second number of virtual DRAM devices comprises two or more physical memory banks of at least two physical DRAM devices of the first number of physical DRAM devices.

16. A method, comprising:

communicating with a first number of physical dynamic random access memory (“

DRAM”

) devices and a memory controller, wherein each of the physical DRAM devices is an individual and independent monolithic device;

interfacing the first number of physical DRAM devices via multiple data paths including a first data path and a distinct second data path to simulate a different, second number of virtual DRAM devices as presented to the memory controller, wherein each of the virtual DRAM devices is an individual and independent monolithic device;

simulating a first virtual DRAM device using a first physical DRAM device on the first data path and a second physical DRAM device on the distinct second data path;

using both a physical row of the first physical DRAM device and a physical row of the second physical DRAM device to simulate a virtual row of the first virtual DRAM device;

receiving a row-access command from the memory controller, directed to the first virtual DRAM device, for the virtual row of the first virtual DRAM device;

based on the received row-access command, translating the received row-access command for the virtual row to a first row access command for the physical row of the first physical DRAM device and a second row access command for the physical row of the second physical DRAM device; and

issuing the first row access command and the second row access command to activate the physical row of the first physical DRAM device and the physical row of the second physical DRAM device, respectively, before a subsequent column-access command is received from the memory controller to access a part of the simulated row that corresponds to the physical row of the first physical DRAM device or the physical row of the second physical DRAM device.

17. The method of claim 16, wherein the virtual row has a virtual row size and each of the physical rows has a physical row size, and the virtual row size is greater than the physical row size.

18. The method of claim 16, further comprising:

interfacing the first number of physical DRAM devices to the memory controller such that first command scheduling constraints are met, wherein the first number of physical DRAM devices are associated with the first command scheduling constraints and the different, second number of virtual DRAM devices are associated with second command scheduling constraints different from the first command scheduling constraints.

19. The method of claim 18, wherein the first command scheduling constraints and the second command scheduling constraints include intra-device command scheduling constraints.

20. The method of claim 18, wherein the first command scheduling constraints and the second command scheduling constraints include inter-device command scheduling constraints.