Storage device, memory controller, and control method

• US 9,727,461 B2
• Filed: 03/02/2015
• Issued: 08/08/2017
• Est. Priority Date: 06/16/2014
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hidaka, Fumitoshi, Aoki, Masatoshi, Kakiki, Itaru, Yokoyama, Tomoki, Nakao, Kaori
• Primary Examiner(s): Lane, John A
• Application Number:
  US14/636,164
• Publication Number:
  US 20150363105A1
• Time in Patent Office: 890 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A storage device includes a first nonvolatile memory that includes memory cells, each capable of storing data of a first number of bits, a second nonvolatile memory of which memory capacity is larger than a memory capacity of the first nonvolatile memory, and a memory controller is configured to control the first nonvolatile memory to store data of a second number of bits that is smaller than the first number in each of at least a part of the memory cells according to a usage amount of the memory cells.

Claims

1. A storage device, comprising:

a first nonvolatile memory that includes a plurality of memory cells;

a second nonvolatile memory of which memory capacity is larger than a memory capacity of the first nonvolatile memory; and

a memory controller configured to control data writing with respect to the first nonvolatile memory, and switch a data writing manner for a part of the memory cells from a first data writing manner according to which data of a first number of bits are written in each memory cell of the part, to a second data writing manner according to which data of a second number of bits that is smaller than the first number are written in each memory cell of the part, according to a usage amount of the part of the memory cells.

2. The storage device according to claim 1, wherein

the usage amount is indicated by a number of times data have been written in the part of the memory cells.

3. The storage device according to claim 1, wherein

the memory controller is further configured to cause data stored in the part of the memory cells to be read out, and

the usage amount is indicated by a bit length of error correction data corresponding to data read out from the part of the memory cells.

4. The storage device according to claim 1, wherein

the memory controller is configured to cause system data to be written in the first nonvolatile memory according to the first writing manner, and cache data to be written in the first nonvolatile memory according to the second writing manner.

5. The storage device according to claim 1, wherein

the first nonvolatile memory is a NAND-type semiconductor memory.

6. The storage device according to claim 5, wherein

the second nonvolatile memory is a magnetic memory.

7. The storage device according to claim 1, wherein

the first number is equal to or greater than two, and the second number is one.

8. A memory controller of a nonvolatile memory that includes a plurality of memory cells, the memory controller comprising:

a memory interface configured to transmit data to the nonvolatile memory and receive data from the nonvolatile memory; and

a control circuit configured to control data writing with respect to the first nonvolatile memory, and switch a data writing manner for a part of the memory cells from a first data writing manner according to which data of a first number of bits are written in each memory cell of the part, to a second data writing manner according to which data of a second number of bits that is smaller than the first number are written in each memory cell of the part, according to a usage amount of the part of the memory cells.

9. The memory controller according to claim 8, wherein

the usage amount is indicated by a number of times data have been written in the part of the memory cells.

10. The memory controller according to claim 8, wherein

the usage amount is indicated by a bit length of error correction data corresponding to data read from the part of the memory cells.

11. The memory controller according to claim 8, wherein

the control circuit is configured to cause system data to be written in the nonvolatile memory according to the first writing manner, and cache data to be written in the nonvolatile memory according to the second writing manner.

12. The memory controller according to claim 8, wherein

the nonvolatile memory is a NAND-type semiconductor memory.

13. The memory controller according to claim 8, wherein

the first number is equal to or greater than two, and the second number is one.

14. A method for controlling a storage device having a first nonvolatile memory that includes a plurality of memory cells, and a second nonvolatile memory of which memory capacity is larger than a memory capacity of the first nonvolatile memory, the method comprising:

controlling data writing with respect to the first nonvolatile memory; and

switching a data writing manner for a part of the memory cells from a first data writing manner according to which data of a first number of bits are written in each memory cell of the part, to a second data writing manner according to which data of a second number of bits that is smaller than the first number are written in each memory cell of the part, according to a usage amount of the part of the memory cells.

15. The method according to claim 14, further comprising:

reading out data stored in the part of the memory cells; and

determining a bit length of error correction data corresponding to read data, wherein

the usage amount is indicated by the bit length.

16. The method according to claim 14, further comprising:

determining a number of times data have been written in the part of the memory cells, wherein

the usage amount is indicated by the number of times.

17. The method according to claim 14, wherein

system data are written in the first nonvolatile memory according to the first writing manner, and cache data are written in the first nonvolatile memory according to the second writing manner.

18. The method according to claim 14, wherein

the first nonvolatile memory is a NAND-type semiconductor memory.

19. The method according to claim 18, wherein

the second nonvolatile memory is a magnetic memory.

20. The method according to claim 14, wherein

the first number is equal to or greater than two, and the second number is one.