Tracking memory accesses when invalidating effective address to real address translations

• US 9,727,483 B2
• Filed: 06/01/2015
• Issued: 08/08/2017
• Est. Priority Date: 12/19/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Blaner, Bartholomew, Heaslip, Jay G., Lauricella, Kenneth A., Stuecheli, Jeffrey A.
• Primary Examiner(s): Yi, David X
• Assistant Examiner(s): Talukdar, Arvind
• Application Number:
  US14/727,075
• Publication Number:
  US 20160179698A1
• Time in Patent Office: 799 Days
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 2212/657 Virtual address space management

Abstract

According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.

Claims

1. A method, implemented in a computing system having both a memory management unit with a translation lookaside buffer (TLB) and a central processing unit (CPU) with an effective address to real address translation (ERAT) unit having an ERAT table and corresponding set of counters, for tracking address translation entries in the ERAT table, the method comprising:

storing, by the ERAT unit, a set of effective address to real address translations in entries of the ERAT table, wherein the ERAT table includes an entry for each effective address to real address translation in the set of effective address to real address translations and the corresponding set of counters includes a counter corresponding to each ERAT entry;

receiving, by the ERAT unit, a request to execute a memory operation;

determining, by the ERAT unit, whether the request to execute a memory operation is one of a memory access request and an address invalidation request, wherein

the memory access request is received from an execution unit within the CPU to cause the ERAT unit to provide a first effective address to real address translation to a first memory access entity (MAE) of a set of two or more memory access entities (MAEs) in the CPU, the request including a first identifier of the first MAE, and

the address invalidation request is received from a memory management unit (MMU) external to the CPU to cause the ERAT unit to stop using a second effective address to real address translation stored in the ERAT table to translate effective addresses;

determining, in response to determining that the request to execute a memory operation is a memory access request, that the first effective address to real address translation is stored in the ERAT table in a first ERAT table entry having a first ERAT table index;

storing, by the ERAT unit, the first ERAT table index in a first tracking array entry of a tracking array having entries with indexes corresponding to each identifier of each MAE in the set of two or more MAEs, wherein the first tracking array entry has an index corresponding to the first identifier;

incrementing, by the ERAT unit, a first counter associated with the first ERAT table entry;

receiving, by the ERAT unit from a second MAE, an indication that the second MAE has completed a memory access using a third effective to real address translation, the indication including a second identifier of the second MAE;

retrieving, by the ERAT unit from the tracking array using the second identifier, a second ERAT table index corresponding to a second ERAT table entry providing the third effective to real address translation; and

identifying, by the ERAT unit using the second ERAT table index, a second counter associated with the second ERAT table entry and decrementing the second counter.

2. The method of claim 1, further comprising:

identifying, in response to determining that the request to execute a memory operation is an address invalidation request and based on a first effective address and a first process identifier included in the address invalidation request, a third ERAT table entry having the second effective to real address translation;

determining, by the ERAT unit, that a third counter associated with the third ERAT table entry indicates that the second effective to real address translation is not being used by any of the set of two or more MAEs; and

invalidating, by the ERAT unit, the second effective to real address translation in the ERAT table in response to determining that the second effective to real address translation is not being used by any of the set of two or more MAEs.

3. The method in claim 1, further comprising:

identifying, in response to determining that the request to execute a memory operation is an address invalidation request and based on a first effective address and a first process identifier included in the address invalidation request, a third ERAT table entry having the second effective to real address translation;

determining, by the ERAT unit, that a third counter associated with the third ERAT table entry indicates that the second effective to real address translation is being used by at least one MAE; and

stalling, by the ERAT unit and in response to determining that the second effective to real address translation request is being used by at least one MAE, execution of the address invalidation request.

4. The method in claim 1, wherein the counter is a one-bit counter.

5. The method in claim 1, wherein the tracking array tracks translations used by an MAE in the set of two or more MAEs.

6. The method in claim 5, wherein the tracking array comprises a plurality of elements, each element associated with one of the set of two or more MAEs.

7. The method in claim 1, wherein the address invalidation request includes a request to invalidate a plurality of address translations.