Two dimensional magnetic recording system, devices and methods

• US 9,728,221 B2
• Filed: 08/12/2016
• Issued: 08/08/2017
• Est. Priority Date: 06/26/2014
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Oberg, Mats, Nangare, Nitin
• Primary Examiner(s): HINDI, NABIL Z
• Application Number:
  US15/236,023
• Publication Number:
  US 20160351225A1
• Time in Patent Office: 361 Days
• Field of Search: 360 39, 360 51, 360 75, 360 7714, 360 7308, 360 7307, 360 65, 360 7304, 369 471, 369 4727, 369 4437
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/10037 A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
• CPC Class Codes: G11B 20/10046 filtering or equalising, e.g. setting the tap weights of an FIR filter
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs
• CPC Class Codes: G11B 5/012 Recording on, or reproducing or erasing from, magnetic disks G11B17/00, G11B19/00 take precedence
• CPC Class Codes: G11B 5/02 Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
• CPC Class Codes: G11B 5/3964 for transducing on a single track
• CPC Class Codes: G11B 5/4976 Disposition of heads, e.g. matrix arrangement

Abstract

This application includes systems and techniques relating to storage devices, such as a device including: a first read channel to process a first input signal obtained from a storage medium using a first read head; a second read channel to process a second input signal obtained from the storage medium using a second read head, which is offset from the first read head in each of two dimensions; a single digital timing loop configured to control interpolation of timing of sampling for first and second analog to digital converters in the first and second read channels; and a two dimensional equalizer coupled with output lines of the first and second read channels; the device being configured to account for a fractional timing difference between the first input signal and the second input signal, the fractional timing difference being a fractional amount of a single clock cycle of the device.

Claims

1. A device comprising:

a first read channel to process a first input signal obtained from a storage medium using a first read head, wherein the first read channel comprises a first analog to digital converter;

a second read channel to process a second input signal obtained from the storage medium using a second read head, wherein the second read channel comprises a second analog to digital converter;

a single digital timing loop for both the first read channel and the second read channel, wherein the single digital timing loop is configured to control interpolation of timing of sampling for the first and second analog to digital converters; and

a two dimensional equalizer coupled with output lines of the first read channel and the second read channel;

wherein the first read head and the second read head are offset from each other in each of two dimensions; and

wherein the device is configured to account for a fractional timing difference between the first input signal and the second input signal, the fractional timing difference being a fractional amount, less than one, of a single clock cycle of the device.

2. The device of claim 1, comprising:

a first interpolator for the first analog to digital converter, the first interpolator coupled with the single digital timing loop for control of the first interpolator by the single digital timing loop; and

a second interpolator for the second analog to digital converter, the second interpolator coupled with the single digital timing loop for control of the second interpolator by the single digital timing loop;

wherein the first and second interpolators are configured to account for the fractional timing difference between the first input signal and the second input signal.

3. The device of claim 2, wherein each of the first and second interpolators has a resolution of 1/128 of the single clock cycle.

4. The device of claim 2, wherein the first read channel further comprises a first asymmetry correction block, a first variable gain amplifier, and a first programmable delay line;

the second read channel further comprises a second asymmetry correction block, a second variable gain amplifier, and a second programmable delay line; and

the device further comprises;

an adaptive finite impulse response unit lying outside of the first and second read channels; and

a baseline unit configured to generate an error signal to control the adaptive finite impulse response unit, the variable gain amplifiers, and the single digital timing loop.

5. The device of claim 4, wherein:

the first read channel further comprises a first finite impulse response filter coupled with the adaptive finite impulse response unit;

the second read channel further comprises a second finite impulse response filter; and

the device is configured to copy finite impulse response filter taps for the first finite impulse response filter from the first finite impulse response filter to the second finite impulse response filter.

6. The device of claim 4, further comprising a finite impulse response filter lying outside of the first and second read channels, the finite impulse response filter having an input line coupled with an output line of the first programmable delay line, and the finite impulse response filter being coupled between the adaptive finite impulse response unit and the baseline unit to generate the error signal.

7. The device of claim 2, wherein:

the first read channel further comprises a first asymmetry correction block, a first variable gain amplifier, and a first programmable delay line;

the second read channel further comprises a second asymmetry correction block, a second variable gain amplifier, and a second programmable delay line; and

the device is configured to generate an error signal from an output of the two dimensional equalizer to drive the variable gain amplifiers and the single digital timing loop.

8. The device of claim 1, wherein the device is configured to adjust coefficients on taps of respective finite impulse response filters in the two dimensional equalizer to account for the fractional timing difference between the first input signal and the second input signal.

9. A system comprising:

a storage apparatus comprising a magnetic media disk, which is mounted on a spindle and motor assembly, and a head assembly comprising at least a first read head and a second read head, wherein the first read head and the second read head are offset from each other in each of two dimensions; and

a storage controller coupled with the storage apparatus, the storage controller comprising a first read channel to process a first input signal obtained from the magnetic media disk of the storage apparatus using the first read head, and a second read channel to process a second input signal obtained from the magnetic media disk of the storage apparatus using the second read head;

wherein the first read channel comprises a first analog to digital converter, the second read channel comprises a second analog to digital converter; and

wherein the storage controller comprises a single digital timing loop for both the first read channel and the second read channel, the single digital timing loop being configured to control interpolation of timing of sampling for the first and second analog to digital converters, the storage controller comprises a two dimensional equalizer coupled with output lines of the first read channel and the second read channel, and the storage controller is configured to account for a fractional timing difference between the first input signal and the second input signal, the fractional timing difference being a fractional amount, less than one, of a single clock cycle of the device.

10. The system of claim 9, wherein the storage controller comprises:

a first interpolator for the first analog to digital converter, the first interpolator coupled with the single digital timing loop for control of the first interpolator by the single digital timing loop; and

a second interpolator for the second analog to digital converter, the second interpolator coupled with the single digital timing loop for control of the second interpolator by the single digital timing loop;

wherein the first and second interpolators are configured to account for the fractional timing difference between the first input signal and the second input signal.

11. The system of claim 10, wherein each of the first and second interpolators has a resolution of 1/128 of the single clock cycle.

12. The system of claim 10, wherein the first read channel further comprises a first asymmetry correction block, a first variable gain amplifier, and a first programmable delay line;

the second read channel further comprises a second asymmetry correction block, a second variable gain amplifier, and a second programmable delay line; and

the storage controller further comprises;

an adaptive finite impulse response unit lying outside of the first and second read channels; and

a baseline unit configured to generate an error signal to control the adaptive finite impulse response unit, the variable gain amplifiers, and the single digital timing loop.

13. The system of claim 12, wherein:

the first read channel further comprises a first finite impulse response filter coupled with the adaptive finite impulse response unit;

the second read channel further comprises a second finite impulse response filter; and

the storage controller is configured to copy finite impulse response filter taps for the first finite impulse response filter from the first finite impulse response filter to the second finite impulse response filter.

14. The system of claim 12, wherein the storage controller further comprises a finite impulse response filter lying outside of the first and second read channels, the finite impulse response filter having an input line coupled with an output line of the first programmable delay line, and the finite impulse response filter being coupled between the adaptive finite impulse response unit and the baseline unit to generate the error signal.

15. The system of claim 10, wherein:

the first read channel further comprises a first asymmetry correction block, a first variable gain amplifier, and a first programmable delay line;

the second read channel further comprises a second asymmetry correction block, a second variable gain amplifier, and a second programmable delay line; and

the storage controller is configured to generate an error signal from an output of the two dimensional equalizer to drive the variable gain amplifiers and the single digital timing loop.

16. The system of claim 9, wherein the storage controller is configured to adjust coefficients on taps of respective finite impulse response filters in the two dimensional equalizer to account for the fractional timing difference between the first input signal and the second input signal.

17. A method comprising:

processing, in a first read channel, a first input signal obtained from a storage medium using a first read head, wherein the first read channel comprises a first analog to digital converter;

processing, in a second read channel, a second input signal obtained from the storage medium using a second read head, wherein the second read channel comprises a second analog to digital converter, and the first read head and the second read head are offset from each other in each of two dimensions;

controlling interpolation of timing of sampling for the first and second analog to digital converters using a single digital timing loop for both the first read channel and the second read channel;

performing two dimensional equalization on outputs of the first read channel and the second read channel; and

accounting for a fractional timing difference between the first input signal and the second input signal, the fractional timing difference being a fractional amount, less than one, of a single clock cycle.

18. The method of claim 17, wherein the accounting comprises using two separate interpolators coupled with the single digital timing loop.

19. The method of claim 17, wherein the first read channel further comprises a first asymmetry correction block, a first variable gain amplifier, and a first programmable delay line;

the second read channel further comprises a second asymmetry correction block, a second variable gain amplifier, and a second programmable delay line; and

the method comprises;

generating an error signal from an output of the two dimensional equalization to drive the variable gain amplifiers and the single digital timing loop.

20. The method of claim 17, wherein the accounting comprises adjusting coefficients on taps of respective finite impulse response filters performing the two dimensional equalization.