Semiconductor structure and memory device including the structure

• US 9,728,248 B2
• Filed: 03/13/2015
• Issued: 08/08/2017
• Est. Priority Date: 03/21/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Tailliet, Franois, Battista, Marc
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Techane, Muna A
• Application Number:
  US14/657,914
• Publication Number:
  US 20150269989A1
• Time in Patent Office: 879 Days
• Field of Search: 36518507
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.

Claims

1. A memory device, comprising:

an SRAM elementary memory cell comprising a first inverter cross-coupled with a second inverter, each of the first inverter and the second inverter comprising a first transistor, a second transistor coupled in series with the first transistor, and an integrated structure, the integrated structure comprising;

a MOS transistor comprising a first gate dielectric and a gate region over the first gate dielectric, the MOS transistor being the second transistor of a respective one of the first inverter and the second inverter;

a capacitor comprising a first capacitor electrode formed by the gate region of the MOS transistor, a second dielectric over the first capacitor electrode, and a second capacitor electrode over the second dielectric, wherein the second capacitor electrode is connected to a potential node;

a first electrically conductive contact region in electrical contact with the gate region of the MOS transistor; and

a second electrically conductive contact region in electrical contact with the second capacitor electrode, wherein the first electrically conductive contact region and the second electrically conductive contact region are not electrically connected to one another; and

a nonvolatile elementary memory cell comprising a floating-gate transistor, the floating-gate transistor having a drain terminal coupled to an output of the first inverter and an input of the second inverter, wherein the SRAM elementary memory cell and the nonvolatile elementary memory cell together form a memory cell.

2. The device according to claim 1, wherein the first transistor of each of the first inverter and the second inverter comprises a gate region surmounted by an auxiliary region located in the same level as the second capacitor electrodes of the integrated structures and separated from the gate region by the second dielectric.

3. The device according to claim 1, wherein the MOS transistor of each of the first inverter and the second inverter comprises a pMOS transistor.

4. The device according to claim 1, wherein each second electrode is coupled to respective output of one of the two inverters.

5. The device according to claim 1, wherein each second electrode is coupled to a reference voltage node.

6. The device according to claim 1, wherein the nonvolatile elementary memory cell is coupled between a power supply terminal and the SRAM elementary memory cell, the floating-gate transistor of the nonvolatile elementary memory cell being controllable so that it is turned off during an operation for programming a datum stored in the SRAM elementary memory cell into the nonvolatile elementary memory cell.

7. The device according to claim 1, wherein the memory device comprises two groups of memory cells that each comprise a nonvolatile elementary memory cell with a floating-gate transistor;

wherein all the floating-gate transistors having a first conduction electrode coupled to a power supply terminal and a control electrode connected to a first control line;

wherein a second conduction electrode of each floating-gate transistor of the nonvolatile elementary memory cells of the two groups is coupled to at least outputs of two inverters, respectively, by way of a controllable interconnect stage; and

wherein the floating-gate transistors controllable so that they are all turned off during a differential operation for programming a datum stored in the SRAM elementary memory cell into the two groups of memory cells.

8. The device according to claim 1, wherein the second dielectric comprises a silicon nitride layer sandwiched between two silicon dioxide layers.

9. The device according to claim 1, wherein the nonvolatile elementary memory cell is an EEPROM cell.

10. The device according to claim 1, wherein the device comprises a memory plane containing rows and columns of memory cells, each memory cell including an SRAM elementary memory cell and a nonvolatile elementary memory cell.

11. A memory cell comprising:

a non-volatile memory cell;

a first inverter comprising a first transistor and a first integrated transistor/capacitor coupled in series between a VDD node and a ground node, wherein the first integrated transistor/capacitor comprises a first MOS transistor with a gate and a capacitor that includes the gate and an electrode above the gate, the electrode being electrically coupled to a first portion of the non-volatile memory cell, the first MOS transistor being a second transistor of the first inverter;

a second inverter comprising a second transistor and a second integrated transistor/capacitor coupled in series between the VDD node and the ground node, wherein the second integrated transistor/capacitor comprises a second MOS transistor with a gate and a capacitor that includes the gate and an electrode above the gate, the electrode being coupled to a second portion of the non-volatile memory cell, the second MOS transistor being a second transistor of the second inverter, an output of the second inverter being coupled to an input of the first inverter including the gate of the first MOS transistor, and an input of the second inverter including the gate of the second MOS transistor being coupled to an output of the first inverter.

12. The memory cell according to claim 11, wherein each integrated transistor/capacitor comprises:

a first source/drain region;

a second source drain region spaced from the first source/drain region by a channel region, wherein the gate overlies the channel region and the electrode is disposed above the gate;

a first dielectric disposed between the gate and the channel region;

a second dielectric disposed between the gate and the electrode;

a first electrically conductive contact region in electrical contact with the gate; and

a second electrically conductive contact region in electrical contact with the electrode, the first and second contact regions being electrically isolated from one another.

13. The memory cell according to claim 11, wherein the electrode of the first integrated transistor/capacitor is coupled to the output of the first inverter and wherein the electrode of the second integrated transistor/capacitor is coupled to the output of the second inverter.

14. The memory cell according to claim 11, wherein the electrode of the first integrated transistor/capacitor and the electrode of the second integrated transistor/capacitor are both coupled to the VDD node.

15. The memory cell according to claim 11, wherein the electrode of the first integrated transistor/capacitor and the electrode of the second integrated transistor/capacitor are both coupled to the ground node.

16. The memory cell according to claim 11, wherein the first MOS transistor comprises a pMOS transistor and the second MOS transistor comprises a pMOS transistor.

17. The memory cell according to claim 11, wherein the memory cell comprises a single non-volatile memory cell that is coupled between the VDD node and the first inverter, the non-volatile memory cell having a floating-gate transistor that is controllable so that it is turned off during an operation for programming a datum stored by the first and second inverters into the non-volatile memory cell.

18. The memory cell according to claim 11, wherein the non-volatile memory cell comprises an EEPROM cell.

19. A memory device comprising:

an SRAM-type elementary memory cell comprising a first inverter comprising a first transistor coupled in series with a first integrated transistor/capacitor, wherein the first integrated transistor/capacitor comprises a first MOS transistor with a gate and a capacitor that includes the gate and an electrode above the gate, the SRAM-type elementary memory cell also comprising a second inverter comprising a second transistor coupled in series with a second integrated transistor/capacitor, wherein the second integrated transistor/capacitor comprises a second MOS transistor with a gate and a capacitor that includes the gate and an electrode above the gate, the first and second inverters being cross-coupled;

a first non-volatile memory unit having a first non-volatile elementary memory cell with a first floating-gate transistor, the first floating-gate transistor having a first conduction electrode coupled to a supply terminal, a control electrode coupled to a first control line, and a second conduction electrode; and

a second non-volatile memory unit having a second non-volatile elementary memory cell with a second floating-gate transistor, the second floating-gate transistor having a first conduction electrode coupled to the supply terminal, a control electrode coupled to the first control line, and a second conduction electrode;

a controllable interconnection stage with a first portion coupled between the second conduction electrode of the first floating-gate transistor and an output of the first inverter and a second portion coupled between the second conduction electrode of the second floating-gate transistor and an output of the second inverter; and

a control circuit configured to cause the first and second floating-gate transistors to off when a data item stored in the elementary memory cell is differentially programmed into the first and second non-volatile memory units.