Memory device including multiple select gates and different bias conditions

• US 9,728,266 B1
• Filed: 07/08/2016
• Issued: 08/08/2017
• Est. Priority Date: 07/08/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Changhyun, Liu, Haitao, Goda, Akira
• Primary Examiner(s): Tran, Michael
• Application Number:
  US15/205,574
• Time in Patent Office: 396 Days
• Field of Search: 36518915, 36518524
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

Claims

1. An apparatus comprising:

a conductive line;

a first memory cell string and a second memory cell string; and

a first select gate and a second select gate coupled in series between the conductive line and the first memory cell string, the first select gate being located in a first level of the apparatus, the second gate being located in a second level of the apparatus;

a third select gate and a fourth select gate coupled in series between the conductive line and the second memory cell string, the third select gate being located in the first level, the fourth select gate being located in the second level;

a first select line to provide a first voltage to the first select gate during an operation of the apparatus;

a second select line to provide a second voltage to the second select gate during the operation, the first and second voltages having a same value;

a third select line to provide a third voltage to the third select gate during the operation;

a fourth select line to provide a fourth voltage to the fourth select gate during the operation, the third and fourth voltages having different values;

first control lines coupled to the first memory cell string; and

second control lines coupled to the second memory cell string, the second control lines being different from the first control lines, and the operation includes one of an operation of storing information in a memory cell of the first memory cell string and an operation of reading information from a memory cell of the first memory cell string.

2. An apparatus comprising:

a conductive line;

a first memory cell string and a second memory cell string; and

a first select gate and a second select gate coupled in series between the conductive line and the first memory cell string, the first select gate being located in a first level of the apparatus, the second gate being located in a second level of the apparatus;

a third select gate and a fourth select gate coupled in series between the conductive line and the second memory cell string, the third select gate being located in the first level, the fourth select gate being located in the second level;

a first select line to provide a first voltage to the first select gate during an operation of the apparatus;

a second select line to provide a second voltage to the second select gate during the operation, the first and second voltages having a same value;

a third select line to provide a third voltage to the third select gate during the operation; and

a fourth select line to provide a fourth voltage to the fourth select gate during the operation, the third and fourth voltages having different values, wherein;

the first select line is to provide a fifth voltage to the first select gate during an additional operation of the apparatus;

the second select line is to provide a sixth voltage to the second select gate during the additional operation, the fifth and sixth voltages having a same value;

the third select line is to provide a seventh voltage to the third select gate during the additional operation; and

the fourth select line is to provide an eighth voltage to the fourth select gate during the additional operation, the seventh and eighth voltages having a same value, and the fifth and seventh voltages having different values.

3. An apparatus comprising:

a conductive line;

a first memory cell string and a second memory cell string; and

a first select Rate and a second select gate coupled in series between the conductive line and the first memory cell string, the first select gate being located in a first level of the apparatus, the second gate being located in a second level of the apparatus;

a third select gate and a fourth select gate coupled in series between the conductive line and the second memory cell string, the third select gate being located in the first level, the fourth select gate being located in the second level;

a first select line to provide a first voltage to the first select gate during an operation of the apparatus;

a second select line to provide a second voltage to the second select gate during the operation, the first and second voltages having a same value;

a third select line to provide a third voltage to the third select gate during the operation;

a fourth select line to provide a fourth voltage to the fourth select gate during the operation, the third and fourth voltages having different values; and

a substrate, wherein the first memory cell string is located between the substrate and the first and second select gates.

4. The apparatus of claim 3, further comprising control lines shared by the first and second memory cell strings, and the operation includes one of an operation of storing information in a memory cell of the first memory cell string and an operation of reading information from a memory cell of the memory cell string.

5. The apparatus of claim 3, wherein the first and third voltages are provided by a same signal of the apparatus.

6. The apparatus of claim 3, wherein the first and third voltages are provided by different signals of the apparatus.

7. The apparatus of claim 3, wherein each of the first, second, third, and fourth select gates includes a charge storage element.

8. The apparatus of claim 3, wherein each of the first and second memory cell strings includes a memory cell, the memory cell including a floating-gate memory cell structure.

9. The apparatus of claim 3, wherein each of the first and second memory cell strings includes a memory cell, the memory cell including a charge-trap memory cell structure.

10. An apparatus comprising:

a conductive line;

a first memory cell string and a second memory cell string; and

a first select gate and a second select gate coupled in series between the conductive line and the first memory cell string, the first select gate being located in a first level of the apparatus, the second gate being located in a second level of the apparatus;

a third select gate and a fourth select gate coupled in series between the conductive line and the second memory cell string, the third select gate being located in the first level, the fourth select gate being located in the second level;

a first select line to provide a first voltage to the first select gate during an operation of the apparatus;

a second select line to provide a second voltage to the second select gate during the operation, the first and second voltages having a same value;

a third select line to provide a third voltage to the third select gate during the operation; and

a fourth select line to provide a fourth voltage to the fourth select gate during the operation, the third and fourth voltages having different values, wherein the apparatus comprises a memory device, the memory device including a first block of memory cells and a second block of memory cells, the first memory string included in the first block of memory cells, the second memory cell string included in the second block of memory cells and wherein the third voltage has a value greater than a value of the fourth voltage during the operation if the second block of memory cells is a deselected block.

11. An apparatus comprising:

a conductive line;

a first memory cell string and a second memory cell string; and

a first select Rate and a second select Rate coupled in series between the conductive line and the first memory cell string, the first select gate being located in a first level of the apparatus, the second gate being located in a second level of the apparatus;

a third select gate and a fourth select gate coupled in series between the conductive line and the second memory cell string, the third select gate being located in the first level, the fourth select gate being located in the second level;

a first select line to provide a first voltage to the first select gate during an operation of the apparatus;

a second select line to provide a second voltage to the second select gate during the operation, the first and second voltages having a same value;

a third select line to provide a third voltage to the third select gate during the operation; and

a fourth select line to provide a fourth voltage to the fourth select gate during the operation, the third and fourth voltages having different values, wherein the apparatus comprises a memory device, the memory device including a first block of memory cells and a second block of memory cells, the first memory string included in the first block of memory cells, the second memory cell string included in the second block of memory cells, and wherein the third voltage has a value less than a value of the fourth voltage during an erase operation if the second block of memory cells is a selected block.

12. An apparatus comprising:

a conductive line;

a first memory cell string and a second memory cell string; and

a first select gate and a second select Rate coupled in series between the conductive line and the first memory cell string, the first select Rate being located in a first level of the apparatus, the second Rate being located in a second level of the apparatus;

a third select gate and a fourth select gate coupled in series between the conductive line and the second memory cell string, the third select gate being located in the first level, the fourth select Rate being located in the second level;

a first select line to provide a first voltage to the first select Rate during an operation of the apparatus;

a second select line to provide a second voltage to the second select gate during the operation, the first and second voltages having a same value;

a third select line to provide a third voltage to the third select Rate during the operation;

a fourth select line to provide a fourth voltage to the fourth select gate during the operation, the third and fourth voltages having different values; and

a substrate, wherein the first and second select gates are located between the first memory cell string and the substrate.

13. An apparatus comprising:

a conductive line;

a first memory cell string and a second memory cell string; and

a first select Rate and a second select Rate coupled in series between the conductive line and the first memory cell string, the first select gate being located in a first level of the apparatus, the second gate being located in a second level of the apparatus;

a third select gate and a fourth select gate coupled in series between the conductive line and the second memory cell string, the third select gate being located in the first level, the fourth select gate being located in the second level;

a first select line to provide a first voltage to the first select Rate during an operation of the apparatus;

a second select line to provide a second voltage to the second select gate during the operation, the first and second voltages having a same value;

a third select line to provide a third voltage to the third select gate during the operation;

a fourth select line to provide a fourth voltage to the fourth select gate during the operation, the third and fourth voltages having different values

a fifth select gate coupled in series with the first and second select gates between the conductive line and the first memory cell string; and

a sixth select gate coupled in series with the third and fourth select gates between the conductive line and the second memory cell string.

14. An apparatus comprising:

a conductive line;

a first memory cell string and a second memory cell string; and

a first select gate and a second select gate coupled in series between the conductive line and the first memory cell string, the first select gate being located in a first level of the apparatus, the second gate being located in a second level of the apparatus;

a third select gate and a fourth select gate coupled in series between the conductive line and the second memory cell string, the third select gate being located in the first level, the fourth select gate being located in the second level;

a first select line to provide a first voltage to the first select gate during an operation of the apparatus;

a second select line to provide a second voltage to the second select gate during the operation, the first and second voltages having a same value;

a third select line to provide a third voltage to the third select gate during the operation; and

a fourth select line to provide a fourth voltage to the fourth select gate during the operation, the third and fourth voltages having different values, wherein the first select gate includes a first portion and a second portion contacting the first portion, and the first and second portions have different resistances.

15. The apparatus of claim 14, wherein the first portion is a polycrystalline silicon portion and the second portion is one of a metal portion and a silicide portion.

16. An apparatus comprising:

a conductive line;

a first memory cell string and a second memory cell string; and

a first select gate and a second select gate coupled in series between the conductive line and the first memory cell string, the first select gate being located in a first level of the apparatus, the second gate being located in a second level of the apparatus;

a third select gate and a fourth select gate coupled in series between the conductive line and the second memory cell string, the third select gate being located in the first level, the fourth select gate being located in the second level;

a first select line to provide a first voltage to the first select gate during an operation of the apparatus;

a second select line to provide a second voltage to the second select gate during the operation, the first and second voltages having a same value;

a third select line to provide a third voltage to the third select gate during the operation; and

a fourth select line to provide a fourth voltage to the fourth select gate during the operation, the third and fourth voltages having different values, wherein each of the first, second, third, and fourth select gates includes a field-effect transistor structure.

17. A method comprising:

applying a first voltage to a first select line of a memory device during an operation of the memory device, the first select line coupled to a first select gate of the memory device;

applying a second voltage to a second select line of the memory device during the operation, the first and second voltages having a same value, the second select line coupled to a second select gate of the memory device, the first select gate being located in a first level of the apparatus, the second gate being located in a second level of the apparatus, the first and second select gates coupled in series between a data line and the a first memory cell string of the memory device;

applying a third voltage to a third select line of a memory device during the operation, the third select line coupled to the third select gate of the memory device;

applying a fourth voltage to a fourth select line of the memory device during the operation, the third and fourth voltages having different values, the fourth select line coupled to a fourth select gate of the memory device, the third select Rate being located in the first level of the apparatus, the fourth gate being located in the second level of the apparatus, the third and fourth select gates coupled in series between the data line and a second memory cell string of the memory device;

applying a fifth voltage to the first and third select lines during an additional operation of the memory device; and

applying a sixth voltage to the second and fourth select lines of the memory device during the additional operation, the fifth and sixth voltages having different values.

18. The method of claim 17, wherein the first and second memory cells are coupled to same access lines.

19. The method of claim 17, wherein the first and second memory cell strings are coupled to different access lines.

20. The method of claim 17, further comprising:

reading information from a memory cell of the first memory cell string during the operation.

21. The method of claim 17, further comprising:

storing information in a memory cell of the first memory cell string during the operation.