Split-gate non-volatile memory (NVM) cell and method therefor

• US 9,728,410 B2
• Filed: 10/07/2014
• Issued: 08/08/2017
• Est. Priority Date: 10/07/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Perera, Asanga H., Swift, Craig T.
• Primary Examiner(s): Kim, Su C
• Assistant Examiner(s): Wilbert, David S
• Application Number:
  US14/508,629
• Publication Number:
  US 20160099153A1
• Time in Patent Office: 1,036 Days
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence

Abstract

A split gate memory device includes a semiconductor substrate and a select gate over the substrate. The select gate has a bottom portion and a top portion over the bottom portion, wherein the top portion has a top sidewall and the bottom portion has a bottom sidewall, and wherein the bottom sidewall extends beyond the top sidewall. The devices also includes a control gate adjacent the select gate, a charge storage layer located between the select gate and the control gate and between the control gate and the substrate, and an isolation region over the bottom portion of the select gate and between the top sidewall of the select gate and the charge storage layer. The bottom sidewall of the bottom portion extends to the charge storage layer.

Claims

1. A method for forming a split gate memory device, comprising:

forming a select gate of the split gate memory device over a semiconductor substrate having a top portion and a bottom portion, wherein the bottom portion is between the top portion and the semiconductor substrate, and the top portion has a smaller width than the bottom portion;

forming a first insulating layer over the bottom portion of the select gate and adjacent a first sidewall of the top portion of the select gate;

removing portions of the bottom portion of the select gate exposed by the first insulating layer such that a first sidewall of the bottom portion is vertically aligned with a sidewall of the first insulating layer;

forming a charge storage layer of the split gate memory device over the semiconductor substrate and the select gate, and along the sidewall of the first insulating layer and the first sidewall of the bottom portion; and

after forming the charge storage layer, forming a control gate of the split gate memory device over the charge storage layer and adjacent the select gate, wherein;

the charge storage layer is between the first sidewall of the bottom portion and the control gate,

a first isolation region formed from the first insulating layer is between the first sidewall of the top portion and the charge storage layer and not between the first sidewall of the bottom portion and the charge storage layer,

the charge storage layer is between the first isolation region and the control gate, and

after formation of the charge storage layer and the control gate, the top portion remains smaller in width than the bottom portion.

2. The method of claim 1, wherein the forming the first insulating layer comprises:

depositing a layer of insulating material over the semiconductor substrate and the select gate; and

anisotropically etching the layer of insulating material to form the first insulating layer.

3. The method of claim 2, wherein the forming the first insulating layer further comprises:

depositing a liner layer over the semiconductor substrate and the select gate wherein the layer of insulating material is deposited over the liner layer and wherein the anisotropically etching comprises etching the liner layer.

4. The method of claim 1, wherein the forming the charge storage layer comprises:

forming a bottom dielectric layer over the semiconductor substrate and the select gate, and along the sidewall of the first insulating layer and the first sidewall of the bottom portion;

forming a layer of nanocrystals over the bottom dielectric layer; and

forming a top dielectric layer over the layer of nanocrystals.

5. The method of claim 1, further comprising:

forming a second insulating layer over the bottom portion of the select gate and adjacent a second sidewall of the top portion of the select gate, wherein the second sidewall of the top portion is opposite the first sidewall of the top portion.

6. The method of claim 5, wherein the forming the first and second insulating layers comprises:

depositing a layer of insulating material over the semiconductor substrate and the select gate; and

anisotropically etching the layer of insulating material to form the first and second insulating layers.

7. The method of claim 6, wherein prior to the forming the charge storage layer, the method comprises:

removing the second insulating layer.

8. The method of claim 7, wherein the removing portions of the bottom portion of the select gate exposed by the first insulating layer comprises removing portions of the bottom portion of the select gate which extend beyond the second sidewall of the top portion such that the second sidewall of the bottom portion is substantially vertically aligned with the second sidewall of the top portion.

9. The method of claim 1, further comprising:

polishing the select gate and the control gate such that a top surface of the select gate is substantially coplanar with a top surface of the control gate, and wherein a portion of the charge storage layer is exposed between the top portion of the select gate and the control gate.

10. The method of claim 9, wherein after the polishing, the method further comprises:

forming a first silicide layer at the top surface of the select gate; and

forming a second silicide layer at the top surface of the control gate.

11. The method of claim 10, further comprising:

forming an interlayer dielectric layer around the select gate and the control gate.

12. A method for forming a split gate memory device, comprising:

forming a first conductive layer of the split gate memory device over a semiconductor substrate;

etching the first conductive layer to form a top portion and a bottom portion of the first conductive layer, wherein the bottom portion is between the top portion and the semiconductor substrate, and the top portion has a smaller width than the bottom portion;

forming an insulating layer over the first conductive layer;

etching the insulating layer to form a first spacer over the bottom portion of the first conductive layer and adjacent a first sidewall of the top portion of the first conductive layer and a second spacer over the bottom portion of the first conductive layer and adjacent a second sidewall of the top portion, opposite the first sidewall of the top portion;

removing portions of the bottom portion exposed by the first spacer to form a select gate having the top portion and the bottom portion, resulting in a first sidewall of the bottom portion vertically aligned with the first spacer;

forming a charge storage layer of the split gate memory device over the semiconductor substrate, the select gate, and along the first spacer and the first sidewall of the bottom portion;

after forming the charge storage layer, forming a second conductive layer over the charge storage layer; and

after forming the second conductive layer, patterning the second conductive layer to form a control gate of the split gate memory device over the charge storage layer and adjacent the select gate, wherein;

the charge storage layer is between the first sidewall of the bottom portion and the control gate,

the first spacer is between the first sidewall of the top portion and the charge storage layer and not between the first sidewall of the bottom portion and the charge storage layer,

the charge storage layer is between the first spacer and the control gate, and

after formation of the charge storage layer and the control gate, the top portion remains smaller in width than the bottom portion.

13. The method of claim 12, further comprising:

polishing the select gate and the control gate, wherein the polishing exposes a portion of the charge storage layer between the top portion of the select gate and the control gate;

after the polishing, forming a first silicide layer at a top surface of the select gate and forming a second silicide layer at a top surface of the control gate.

14. The method of claim 12, further comprising, prior to the forming the charge storage layer, removing the second spacer, and wherein the removing portions of the bottom portion comprises removing portions of the bottom portion which extend beyond the second sidewall of the top portion.