Method for depositing one or more polycrystalline silicon layers on substrate

• US 9,728,452 B2
• Filed: 03/30/2012
• Issued: 08/08/2017
• Est. Priority Date: 04/04/2011
• Status: Expired due to Fees

• Current Assignee: Okmetic Oyj
• Original Assignee: Okmetic Oyj
• Inventors: Airaksinen, Veli Matti, Makinen, Jari
• Primary Examiner(s): Anya, Igwe U
• Application Number:
  US14/009,838
• Publication Number:
  US 20140061867A1
• Time in Patent Office: 1,957 Days
• Field of Search: 438657
• CPC Class Codes: C23C 16/045 Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• CPC Class Codes: C23C 16/24 Deposition of silicon only
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76882 Reflowing or applying of pressure to better fill the contact hole
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for depositing one or more polycrystalline silicon layers (230c) on a substrate (210) by a chemical vapor deposition in a reactor, includes adjusting a deposition temperature between 605° C.-800° C. in a process chamber of the reactor, and depositing the one or more polycrystalline silicon layers on the substrate by using a silicon source gas including SiH4 or SiH2Cl2, and a dopant gas including BCl3.

Claims

1. A method (100) for forming an electrically conductive via through a substrate (210 410) by a chemical vapour deposition in a reactor, the substrate comprising a hole (226, 420) having aspect ratio greater than 7 in the substrate, the method comprising:

adjusting (140) a deposition temperature between 605°

C.-800°

C. and a deposition pressure below 200 mtorr in a process chamber of the reactor, and

depositing (150) one or more polycrystalline silicon layers (230a, 230b, 230c) inside the hole by using a silicon source gas comprising SiH₄ or SiH₂Cl₂, and a dopant gas comprising BCl₃ so that the one or more polycrystalline silicon layers are deposited directly on a surface of the substrate or a surface of an insulation layer (220) inside the hole in order to form the electrically conductive via through the substrate, wherein the maximum layer thickness of each of the one or more polycrystalline silicon layers is about 3 micrometers.

2. The method of claim 1, wherein the dopant gas comprises a mixture of BCl₃ and another gas comprising He, Ar, N₂, or H₂.

3. The method of claim 2, wherein the method comprises depositing the one or more polycrystalline silicon layers on the substrate in the adjusted deposition temperature and a deposition pressure between 160-170 mtorr by using SiH₄ as a silicon source gas.

4. The method of claim 2, wherein the substrate further comprises a protrusion extending from a surface of the substrate, and the one or more polycrystalline silicon layers are deposited on the protrusion.

5. The method of claim 1, wherein the method comprises depositing the one or more polycrystalline silicon layers on the substrate in the adjusted deposition temperature and a deposition pressure between 160-170 mtorr by using SiH₄ as a silicon source gas.

6. The method of claim 5, wherein the substrate further comprises a protrusion extending from a surface of the substrate, and the one or more polycrystalline silicon layers are deposited on the protrusion.

7. The method of claim 5, wherein the substrate comprises at least an insulating surface layer.

8. The method of claim 1, wherein the reactor is a horizontal hot-wall reactor, and at least one polycrystalline silicon layer is deposited in the deposition temperature between 605°

C.-650°

C. and at least one polycrystalline silicon layer is deposited in the deposition temperature between 650°

C.-750°

C.

9. The method of claim 8, wherein the substrate further comprises a protrusion extending from a surface of the substrate, and the one or more polycrystalline silicon layers are deposited on the protrusion.

10. The method of claim 8, wherein the substrate comprises at least an insulating surface layer.

11. The method of claim 1, wherein the reactor is a vertical reactor and at least one polycrystalline silicon layer is deposited in the deposition temperature between 605°

C.-650°

C. and at least one polycrystalline silicon layer is deposited in the deposition temperature between 650°

C.-750°

C.

12. The method of claim 11, wherein the substrate further comprises a protrusion extending from a surface of the substrate, and the one or more polycrystalline silicon layers are deposited on the protrusion.

13. The method of claim 1, wherein the substrate further comprises a protrusion extending from a surface of the substrate, and the one or more polycrystalline silicon layers are deposited on the protrusion.

14. The method of claim 1, wherein the substrate comprises at least an insulating surface layer.

15. A semiconductor structure (200) comprising:

a substrate (210, 410), which comprises

a hole (226, 420) having aspect ratio greater than 7 in the substrate, and

one or more polycrystalline silicon layers (230a, 230b, 230c) deposited inside the hole and directly on a surface of the substrate or a surface of an insulation layer (220) that is provided by the method of claim 1 and forming an electrically conductive via through the substrate, wherein the maximum layer thickness of the one or more polycrystalline silicon layers is about 3 micrometers.

16. An apparatus (500) comprising the semiconductor structure (200) of claim 15, wherein the maximum layer thickness of the one or more polycrystalline silicon layers is 3 micrometers.

17. The method of claim 1, wherein at least one polycrystalline silicon layer is deposited in the deposition temperature between 605°

C.-650°

C. and at least one polycrystalline silicon layer is deposited in the deposition temperature between 650°

C.-750°

C.

18. The method of claim 1, wherein,

the substrate is a silicon substrate with an unoxidized silicon surface inside the hole or an oxidized silicon surface inside the hole, and

the one or more polycrystalline silicon layers (230a, 230b, 230c) are deposited directly on the unoxidized silicon surface inside the hole or the oxidized silicon surface inside the hole.

19. A method (100) for forming an electrically conductive via through a substrate (210 410) by a chemical vapour deposition in a reactor, the substrate comprising a hole (226, 420) in the substrate, the method comprising:

adjusting (140) a deposition temperature between 605°

C.-800°

C. and a deposition pressure below 200 mtorr in a process chamber of the reactor, and

depositing (150) one or more polycrystalline silicon layers (230a, 230b, 230c) inside the hole by using a silicon source gas comprising SiH₄ or SiH₂Cl₂, and a dopant gas comprising BCl₃ so that the one or more polycrystalline silicon layers are deposited directly on a surface of the substrate or a surface of an insulation layer (220) inside the hole in order to form the electrically conductive via through the substrate,

wherein at least one polycrystalline silicon layer is deposited in the deposition temperature between 605°

C.-650°

C. and at least one polycrystalline silicon layer is deposited in the deposition temperature between 650°

C.-750°

C.