System, structure, and method of manufacturing a semiconductor substrate stack

• US 9,728,457 B2
• Filed: 10/06/2014
• Issued: 08/08/2017
• Est. Priority Date: 05/14/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Hung-Pin, Wu, Weng-Jin, Chiou, Wen-Chih, Yu, Chen-Hua
• Primary Examiner(s): CARPENTER, ROBERT K
• Application Number:
  US14/507,467
• Publication Number:
  US 20150024546A1
• Time in Patent Office: 1,037 Days
• Field of Search: 438977
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.

Claims

1. A method comprising:

etching a recess in a first side of a first substrate, the recess extending partially into the first substrate, the recess adjacent an active region in the first side of the first substrate;

lining the recess with a dielectric material;

filling the lined recess with a first material;

forming contacts over the first side of the first substrate with at least one contact coupled to the active region and at least another contact over and aligned with the first material in the recess;

forming an interconnect layer over the contacts and coupled to the at least one contact and the at least another contact;

forming a bond pad over the interconnect layer;

thinning a second side of the first substrate to expose the dielectric material;

removing the first material from the recess; and

filling the recess with a conductive material, the conductive material in the recess being coupled to the at least another contact.

2. The method of claim 1, wherein the removing the first material from the recess removes substantially all of the first material from the recess and leaves the dielectric material lining the recess.

3. The method of claim 1, wherein filing the recess with a first material further comprises:

forming an etch stop layer in the recess, the etch stop layer being formed of a material selected from a group of materials consisting of Si, Si_xC_y, Si_xN_y, Si_xC_y, Si_xO_y, Si_xO_yN_z; and

forming a second layer over the etch stop layer in the recess, the second layer being formed of a material selected from a group of materials consisting of a nitride, an oxide, a doped polysilicon, or an undoped polysilicon.

4. The method of claim 3, wherein the removing the first material from the recess further comprises:

performing a first etch process to remove the second layer from the recess, the first etch process exposing the etch stop layer; and

performing a second etch process to remove the etch stop layer from the recess, the second etch process exposing the at least another contact.

5. The method of claim 1, wherein the at least another contact comprises a plurality of conductive contacts contacting the conductive material in the recess.

6. The method of claim 1, wherein the removing the first material from the recess further comprises:

forming a passivation layer over the second side of the first substrate and the exposed dielectric material lining the recess;

planarizing the passivation layer and the dielectric material to expose the first material in the recess; and

selectively etching the first material from the recess.

7. The method of claim 1 further comprising:

bonding the first substrate to a second substrate using the bond pad.

8. A method comprising:

forming an active region in a first surface of a first substrate;

etching a recess from the first surface of the first substrate into the first substrate adjacent the active region;

lining the recess with a dielectric material;

filling the lined recess with a sacrificial material, the sacrificial material having a different material composition than the dielectric material;

forming contacts over the first surface of the first substrate, a first contact being coupled to the active region and a second contact over and aligned with the sacrificial material;

forming an interconnect layer over and coupled to the first and second contacts;

forming a bond pad over the interconnect layer, the bond pad being coupled to at least one of the first contact and the second contact;

bonding the first substrate to a second substrate using the bond pad;

thinning the first substrate from a second surface of the first substrate, the second surface being opposite the first surface, the thinning step exposing a portion of the dielectric material lining the recess;

removing the sacrificial material from the recess from the second surface of the first substrate; and

filling the recess with a conductive material to form a through substrate via (TSV) in the first substrate, the second contact being directly coupled to the conductive material of the TSV.

9. The method of claim 8, wherein the removing the sacrificial material from the recess from the second surface of the first substrate removes substantially all of the sacrificial material from the recess and leaves the dielectric material lining the recess.

10. The method of claim 8, wherein the first contact comprises a plurality of conductive contacts contacting the active region, and the second contact comprises a plurality of conductive contacts contacting the conductive material of the TSV.

11. A method comprising:

etching a first side of a first substrate to create a recess adjacent an active region in the first side of the first substrate, at a step before contact etch;

forming a liner layer lining sidewalls and a bottom of the recess, the liner layer comprising a dielectric material;

filling the lined recess with a first material;

forming a contact layer over the first side of the first substrate, the contact layer comprising a plurality of contacts, a first contact of the plurality of contacts being coupled to the active region, a second contact of the plurality of contacts being aligned with the first material in the recess;

forming an interconnect layer over the contact layer, the interconnect layer being coupled to the first contact and the second contact;

forming a bond pad over the interconnect layer, the bond pad being coupled to at least one of the plurality of contacts;

thinning a second side of the first substrate to expose the line layer;

removing the first material from the recess; and

filling the recess with a conductive material to form a through substrate via (TSV), the TSV coupled to the second contact.

12. The method of claim 11, wherein the filling comprises filling the lined recess with a sacrificial material selected from the group consisting of a nitride, an oxide, a doped polysilicon or an undoped polysilicon.

13. The method of claim 11, wherein a third contact of the plurality of contacts is coupled to the active region, and a fourth contact of the plurality of contacts is aligned with the first material in the recess.

14. The method of claim 11, further comprising depositing an etch stop layer in the recess and over the first material before the forming the contact layer.

15. The method of claim 14, further comprises removing the etch stop layer prior to filling the recess with the conductive material.

16. The method of claim 11, wherein the thinning comprises a chemical mechanical planarization (CMP) process followed by a wet etch process.

17. The method of claim 11, wherein the thinning is performed in a single processing step.

18. The method of claim 11, further comprising:

after the thinning and before the removing the first material, forming a passivation layer on the second side of the first substrate; and

planarizing the passivation layer.

19. The method of claim 18, wherein the planarizing stops at the liner layer, wherein the method further comprises performing a wet etch process or a dry etch process to remove a portion of the liner layer such that the first material is exposed.

20. The method of claim 11, further comprises:

after the filling the recess, forming a connection layer over the second side of the first substrate, the connection layer having a conductive feature coupled to the TSV.

21. The method of claim 11 further comprising bonding the first substrate to a second substrate via the bond pad prior to the thinning.