Enhanced density assembly having microelectronic packages mounted at substantial angle to board
First Claim
1. A stacked microelectronic assembly, comprising:
- a plurality of stacked microelectronic packages, each microelectronic package comprising;
a dielectric element having a first major surface defining a plane and a second major surface opposite the first major surface, an interconnect edge surface extending away from the first major surface and an interconnect region adjacent the interconnect edge surface;
a plurality of electrically conductive package contacts at the interconnect region;
a microelectronic element having a front surface overlying and substantially parallel to the major surface, and a plurality of chip contacts at the front surface electrically coupled with the package contacts; and
an encapsulation region having a surface substantially parallel to the first and second major surfaces of the dielectric element;
the plurality of microelectronic packages stacked with one another such that planes defined by the major surfaces of the dielectric elements are substantially parallel to one another, wherein the surface of the encapsulation region of a first microelectronic package of the plurality of microelectronic packages is mechanically coupled with the second major surface of a second microelectronic package of the plurality of microelectronic packages;
a circuit panel having a mounting surface and surface mount panel contacts at the mounting surface, wherein the plurality of package contacts of each package in the stacked microelectronic assembly are electrically coupled via electrically conductive bumps with a corresponding set of the panel contacts at the mounting surface via a ball grid array, wherein the planes defined by the major surfaces of the dielectric elements are oriented at a non-zero angle relative to the mounting surface; and
an underfill surrounding the electrically conductive bumps, the underfill mechanically reinforcing connections between the panel contacts and the plurality of package contacts of each package in the stacked microelectronic assembly.
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Accused Products
Abstract
A microelectronic assembly includes a plurality of stacked microelectronic packages, each comprising a dielectric element having a major surface, an interconnect region adjacent an interconnect edge surface which extends away from the major surface, and plurality of package contacts at the interconnect region. A microelectronic element has a front surface with chip contacts thereon coupled to the package contacts, the front surface overlying and parallel to the major surface. The microelectronic packages are stacked with planes defined by the dielectric elements substantially parallel to one another, and the package contacts electrically coupled with panel contacts at a mounting surface of a circuit panel via an electrically conductive material, the planes defined by the dielectric elements being oriented at a substantial angle to the mounting surface.
323 Citations
19 Claims
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1. A stacked microelectronic assembly, comprising:
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a plurality of stacked microelectronic packages, each microelectronic package comprising; a dielectric element having a first major surface defining a plane and a second major surface opposite the first major surface, an interconnect edge surface extending away from the first major surface and an interconnect region adjacent the interconnect edge surface; a plurality of electrically conductive package contacts at the interconnect region; a microelectronic element having a front surface overlying and substantially parallel to the major surface, and a plurality of chip contacts at the front surface electrically coupled with the package contacts; and an encapsulation region having a surface substantially parallel to the first and second major surfaces of the dielectric element; the plurality of microelectronic packages stacked with one another such that planes defined by the major surfaces of the dielectric elements are substantially parallel to one another, wherein the surface of the encapsulation region of a first microelectronic package of the plurality of microelectronic packages is mechanically coupled with the second major surface of a second microelectronic package of the plurality of microelectronic packages; a circuit panel having a mounting surface and surface mount panel contacts at the mounting surface, wherein the plurality of package contacts of each package in the stacked microelectronic assembly are electrically coupled via electrically conductive bumps with a corresponding set of the panel contacts at the mounting surface via a ball grid array, wherein the planes defined by the major surfaces of the dielectric elements are oriented at a non-zero angle relative to the mounting surface; and an underfill surrounding the electrically conductive bumps, the underfill mechanically reinforcing connections between the panel contacts and the plurality of package contacts of each package in the stacked microelectronic assembly. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A stacked microelectronic package assembly, comprising:
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a plurality of stacked microelectronic packages, each comprising; a dielectric element having a first major surface defining a plane and a second major surface opposite the first major surface, an interconnect edge surface extending away from the first major surface and an interconnect region adjacent the interconnect edge surface; a plurality of electrically conductive package contacts at the interconnect region; a plurality of stacked microelectronic elements each microelectronic element having a front surface defining a plane extending in a first direction and a second direction transverse to the first direction, a plurality of edge surfaces extending away from the plane of the front surface, each microelectronic element having a plurality of chip contacts at the front surface, the microelectronic elements stacked with the planes parallel to one another; and an encapsulation region having a surface substantially parallel to the first and second major surfaces of the dielectric element, wherein the surface of the encapsulation region of a first microelectronic package of the plurality of microelectronic packages is mechanically coupled with the second major surface of a second microelectronic package of the plurality of microelectronic packages, and wherein the package contacts at the interconnect regions of each of the dielectric elements of the stacked microelectronic packages are configured to be bonded via electrically conductive bumps surrounded by an underfill to corresponding surface mount panel contacts at a mounting surface of a circuit panel via a ball grid array, which mounting surface is oriented at a substantial angle relative to the interconnect regions of the dielectric elements, the underfill mechanically reinforcing connections between the panel contacts and the plurality of package contacts of each package in the stacked microelectronic package assembly. - View Dependent Claims (16, 17)
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18. A method of fabricating a stacked microelectronic assembly, comprising:
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fabricating a plurality of microelectronic packages, each comprising; a dielectric element having a major surface defining a plane, an interconnect edge extending away from the major surface and an interconnect region adjacent the interconnect edge, a plurality of electrically conductive package contacts at the interconnect region; and one or more microelectronic elements, each microelectronic element having a memory storage array thereon, and having a front surface defining a plane extending in a first direction and a second direction transverse to the first direction, a plurality of edge surfaces extending away from the plane of the front surface, each microelectronic element having a plurality of chip contacts at the front surface, the plane defined by each microelectronic element parallel to the plane defined by the major surface of the dielectric element of the respective microelectronic package, receiving at least portions of each of the plurality of microelectronic packages into respective slots of a heat spreader element, each slot sized to receive a corresponding individual one of the plurality of microelectronic packages; and bonding the package contacts of each microelectronic package to corresponding panel contacts at a major surface of a circuit panel, wherein the planes defined by the dielectric elements are oriented at a substantial angle relative to the major surface of the circuit panel. - View Dependent Claims (19)
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Specification