Pixel structure

• US 9,728,592 B2
• Filed: 03/09/2016
• Issued: 08/08/2017
• Est. Priority Date: 08/06/2015
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Huang, Chen-Shuo, Chang, Chih-Pang, Li, Hung-Wei
• Primary Examiner(s): Ingham, John C
• Assistant Examiner(s): RAMALLO, GUSTAVO G
• Application Number:
  US15/065,213
• Publication Number:
  US 20170040394A1
• Time in Patent Office: 517 Days
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

A pixel structure includes a metal oxide semiconductor layer, a first insulating layer, a second insulating layer, a first conductive layer, a passivation layer, a second conductive layer and a pixel electrode. The metal oxide semiconductor layer includes a second semiconductor pattern. The first insulating layer includes a first capacitance dielectric pattern disposed on the second semiconductor pattern. The second insulating layer includes a second capacitance dielectric pattern disposed on the first capacitance dielectric pattern. The first conductive layer includes a electrode pattern disposed on the second capacitance dielectric pattern. The passivation layer covers the first conductive layer. The second conductive layer includes a second electrode disposed on the passivation layer. The second electrode is electrically connected to the second semiconductor pattern. The second electrode is disposed to overlap the electrode pattern. The second semiconductor pattern, the electrode pattern and the second electrode form a storage capacitor.

Claims

1. A pixel structure, comprising:

a metal oxide semiconductor layer comprising a first semiconductor pattern and a second semiconductor pattern, wherein the first semiconductor pattern comprises a first doping region, a second doping region and a channel region, the first doping region and the second doping region are disposed respectively on two sides of the channel region, and the second semiconductor pattern comprises a contact portion and an electrode portion;

a first insulating layer comprising a first gate insulation pattern and a first capacitance dielectric pattern, wherein the first gate insulation pattern is disposed on the first semiconductor pattern of the metal oxide semiconductor layer, and the first capacitance dielectric pattern is disposed on the second semiconductor pattern of the metal oxide semiconductor layer;

a second insulating layer comprising a second gate insulation pattern and a second capacitance dielectric pattern, wherein the second gate insulation pattern is disposed on the first gate insulation pattern of the first insulating layer, and the second capacitance dielectric pattern is disposed on the first capacitance dielectric pattern of the first insulating layer;

a first conductive layer comprising a gate and an electrode pattern, wherein the gate is disposed on the second gate insulation pattern of the second insulating layer, and the electrode pattern is disposed on the second capacitance dielectric pattern of the second insulating layer;

a passivation layer covering the metal oxide semiconductor layer and the first conductive layer, and having a first opening through which the first doping region of the first semiconductor pattern is exposed, a second opening through which the second doping region of the first semiconductor pattern is exposed, a third opening through which the contact portion of the second semiconductor pattern is exposed, and a fourth opening through which the electrode pattern of the first conductive layer is exposed;

a second conductive layer disposed on the passivation layer and comprising a first electrode, a second electrode and a second electrode extending portion connected with the second electrode;

wherein;

the first electrode is electrically connected to the first doping region of the first semiconductor pattern through the first opening;

the second electrode is electrically connected to the second doping region of the first semiconductor pattern through the second opening;

the second electrode is electrically connected to the contact portion of the second semiconductor pattern through the third opening;

the gate, the first semiconductor pattern, the first electrode and the second electrode form an active element;

the second semiconductor pattern partially overlaps the electrode pattern of the first conductive layer and is coupled with the electrode pattern of the first conductive layer to form a first storage capacitor; and

the electrode pattern of the first conductive layer partially overlaps the second electrode extending portion and is coupled with the second electrode extending portion to form a second storage capacitor; and

a pixel electrode electrically connected to the second electrode.

2. The pixel structure according to claim 1, wherein the passivation layer is an inorganic dielectric layer.

3. The pixel structure according to claim 1, wherein the second conductive layer further comprises a connection portion which is electrically connected to the electrode pattern of the first conductive layer through the fourth opening of the passivation layer.

4. The pixel structure according to claim 1, further comprising a conductive pattern disposed above the second semiconductor pattern and between the first capacitance dielectric pattern of the first insulating layer and the second capacitance dielectric pattern of the second insulating layer, wherein the second semiconductor pattern partially overlaps the conductive pattern and is coupled with the conductive pattern to form a third storage capacitor, and the conductive pattern partially overlaps the electrode pattern of the first conductive layer and is coupled with the electrode pattern of the first conductive layer to form a fourth storage capacitor.

5. The pixel structure according to claim 1, wherein the passivation layer is an organic dielectric layer.

6. The pixel structure according to claim 1, wherein the passivation layer is an organic planar layer.

7. A pixel structure, comprising:

a metal oxide semiconductor layer comprising a first semiconductor pattern and a second semiconductor pattern, wherein the first semiconductor pattern comprises a first doping region, a second doping region and a channel region, the first doping region and the second doping region are disposed respectively on two sides of the channel region, and the second semiconductor pattern comprises a contact portion and an electrode portion;

a first insulating layer comprising a first gate insulation pattern and a first capacitance dielectric pattern, wherein the first gate insulation pattern is disposed on the first semiconductor pattern of the metal oxide semiconductor layer, and the first capacitance dielectric pattern is disposed on the second semiconductor pattern of the metal oxide semiconductor layer;

a second insulating layer comprising a second gate insulation pattern and a second capacitance dielectric pattern, wherein the second gate insulation pattern is disposed on the first gate insulation pattern of the first insulating layer, and the second capacitance dielectric pattern is disposed on the first capacitance dielectric pattern of the first insulating layer;

a conductive pattern disposed above the second semiconductor pattern and between the first capacitance dielectric pattern of the first insulating layer and the second capacitance dielectric pattern of the second insulating layer;

a first conductive layer comprising a gate and an electrode pattern, wherein the gate is disposed on the second gate insulation pattern of the second insulating layer, the electrode pattern is disposed on the second capacitance dielectric pattern of the second insulating layer, the first doping region and the second doping region of the first semiconductor pattern are exposed, and the contact portion of the second semiconductor pattern is exposed;

a passivation layer covering the metal oxide semiconductor layer and the first conductive layer and having a first opening through which the first doping region of the first semiconductor pattern is exposed, a second opening through which the second doping region of the first semiconductor pattern is exposed, a third opening through which the contact portion of the second semiconductor pattern is exposed, and fourth opening through which the electrode pattern of the first conductive layer is exposed;

a second conductive layer disposed on the passivation layer and comprising a first electrode and a second electrode, wherein the first electrode is electrically connected to the first doping region of the first semiconductor pattern through the first opening;

the second electrode is electrically connected to the second doping region of the first semiconductor pattern through the second opening;

the gate, the first semiconductor pattern, the first electrode and the second electrode form an active element;

the second electrode is electrically connected to the contact portion of the second semiconductor pattern through the third opening;

the second semiconductor pattern partially overlaps the conductive pattern and is coupled with the conductive pattern to form a storage capacitor; and

the conductive pattern partially overlaps the electrode pattern of the first conductive layer and is coupled with the electrode pattern of the first conductive layer to form another storage capacitor; and

a pixel electrode electrically connected to the second electrode.

8. The pixel structure according to claim 7, wherein the electrode pattern is electrically connected to the second electrode through the third opening.

9. The pixel structure according to claim 7, wherein the second conductive layer further comprises a second electrode connection portion, the second electrode connection portion electrically insulated from the second electrode, and the second electrode connection portion, the electrode pattern, the conductive pattern and the electrode portion of the second semiconductor pattern are partially overlapped, and the second electrode is electrically connected to the electrode pattern.

10. The pixel structure according to claim 7, wherein the passivation layer is an inorganic dielectric layer.

11. The pixel structure according to claim 7, wherein the passivation layer is an organic planar layer.

12. A layered structure usable for a pixel structure, comprising:

a metal oxide semiconductor layer comprising a first semiconductor pattern and a second semiconductor pattern, wherein the first semiconductor pattern comprises a first doping region, a second doping region and a channel region, the first doping region and the second doping region are disposed respectively on two sides of the channel region, and the second semiconductor pattern comprises a contact portion and an electrode portion;

a first conductive layer comprising a gate and an electrode pattern, wherein the gate is disposed above the first semiconductor pattern, and at least one gate insulation pattern is formed between the gate and the first semiconductor pattern;

the electrode pattern is disposed above the second semiconductor pattern, and at least one capacitance dielectric pattern is formed between the electrode pattern and the second semiconductor pattern, such that the first doping region and the second doping region of the first semiconductor pattern are exposed, and the contact portion of the second semiconductor pattern is exposed;

a passivation layer covering the metal oxide semiconductor layer and the first conductive layer and having a first opening through which the first doping region of the first semiconductor pattern is exposed, a second opening through which the second doping region of the first semiconductor pattern is exposed, a third opening through which the contact portion is exposed, and a fourth opening through which the electrode pattern is exposed;

a second conductive layer disposed on the passivation layer and comprising a first electrode and a second electrode, wherein the first electrode is electrically connected to the first doping region of the first semiconductor pattern through the first opening;

the second electrode is electrically connected to the second doping region of the first semiconductor pattern through the second opening;

the gate of the first conductive layer, the first semiconductor pattern, the first electrode and the second electrode form an active element;

the second electrode is electrically connected to the contact portion of the second semiconductor pattern through the third opening; and

a pixel electrode electrically connected to the second electrode,

wherein the second semiconductor pattern, the electrode pattern and the second electrode are formed in a partially overlapping mode to form at least two storage capacitors therebetween.

13. The layered structure according to claim 12, wherein the second conductive layer further comprises a connection portion which is electrically connected to the electrode pattern of the first conductive layer through the fourth opening of the passivation layer.

14. The layered structure according to claim 12, wherein the at least two storage capacitors comprise:

a first storage capacitor formed by the second semiconductor pattern partially overlapping the electrode pattern of the first conductive layer; and

a second storage capacitor formed by the second electrode partially overlapping the electrode pattern of the first conductive layer.

15. The layered structure according to claim 14, wherein the second electrode comprises a second electrode extending portion partially overlapping the electrode pattern of the first conductive layer, wherein the second storage capacitor is formed by the second electrode extending portion and at least a portion of the electrode pattern.

16. The layered structure according to claim 12, wherein the at least one gate insulation pattern formed between the gate and the first semiconductor pattern comprises a first gate insulation pattern disposed on the first semiconductor pattern, and a second gate insulation pattern disposed between the gate and the first gate insulation pattern;

and wherein the at least one capacitance dielectric pattern formed between the electrode pattern and the second semiconductor pattern comprises a first capacitance dielectric pattern disposed on the second semiconductor pattern and a second capacitance dielectric pattern disposed between the electrode pattern and the first capacitance dielectric pattern.

17. The layered structure according to claim 16, further comprising a conductive pattern disposed above the second semiconductor pattern and between the first capacitance dielectric pattern and the second capacitance dielectric pattern, wherein the second semiconductor pattern partially overlaps the conductive pattern to form a third storage capacitor, and the conductive pattern partially overlaps the electrode pattern of the first conductive layer to form a fourth storage capacitor.

18. The layered structure according to claim 12, wherein the electrode pattern is electrically connected to the second electrode through the third opening.

19. The layered structure according to claim 12, wherein the passivation layer is an inorganic dielectric layer.

20. The layered structure according to claim 12, wherein the passivation layer is an organic planar layer.