Semiconductor device comprising a field electrode

• US 9,728,614 B2
• Filed: 12/22/2016
• Issued: 08/08/2017
• Est. Priority Date: 07/14/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Siemieniec, Ralf, Blank, Oliver, Laforet, David, Hirler, Franz
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US15/388,245
• Publication Number:
  US 20170104078A1
• Time in Patent Office: 229 Days
• Field of Search: 438270, 438454
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device is manufactured by forming a gate electrode adjacent to a body region in a semiconductor substrate, forming a field plate trench in a main surface of the substrate, the field plate trench having an extension length in a first direction parallel to the main surface, and forming a field electrode and a field dielectric layer in the field plate trench so that the field electrode is insulated from an adjacent drift zone by the field dielectric layer. The extension length of the field plate trench in the first direction is less than double an extension length of the field electrode in a second direction that is perpendicular to the first direction and is parallel to the main surface. The extension length in the first direction is more than half the extension length in the second direction.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a gate electrode adjacent to a body region in a semiconductor substrate;

forming a field plate trench in a main surface of the semiconductor substrate, the field plate trench having an extension length in a first direction parallel to the main surface; and

forming a field electrode in the field plate trench so that the field electrode is insulated from an adjacent drift zone by a field dielectric layer,

wherein the extension length of the field plate trench in the first direction is less than double an extension length of the field electrode in a second direction that is perpendicular to the first direction and parallel to the main surface,

wherein the extension length in the first direction is more than half the extension length in the second direction,

wherein a field plate material of the field electrode has a resistivity in a range from 10⁵ to 10<sup>−

1</sup> Ohm cm.

2. The method of claim 1, further comprising:

forming a source region adjacent to the main surface; and

forming a drain region adjacent to a back side surface of the semiconductor substrate opposite the main surface.

3. The method of claim 1, wherein the field plate material is selected from the group consisting of:

polysilicon doped at a doping concentration between 1E16 cm<sup>−

3</sup> and 1E19 cm<sup>−

3</sup>, semi-insulating polysilicon (SIPOS); and

amorphous silicon carbide.

4. The method of claim 1, further comprising:

forming a gate trench in the main surface of the semiconductor substrate,

wherein the gate electrode is disposed in the gate trench.

5. The method of claim 1, wherein the gate electrode is a planar gate electrode disposed over the main surface of the semiconductor substrate.

6. The method of claim 1, wherein forming the field electrode and the field dielectric layer in the field plate trench comprises:

forming the field dielectric layer only in a lower portion of the field plate trench, so that an upper portion of the field electrode is in contact with an adjacent source region in the semiconductor substrate.

7. The method of claim 1, further comprising:

forming a source plate above the main surface of the semiconductor substrate, the source plate being in direct contact with the field electrode.

8. The method of claim 1, further comprising:

forming an insulating material on the main surface of the semiconductor substrate;

etching a contact hole in the insulating material;

forming a conductive material in the contact hole so as to form a contact plug; and

forming a source plate on the insulating material, the source plate being electrically coupled to the field electrode through the contact plug.

9. A method of manufacturing a semiconductor device, the method comprising:

forming a gate electrode adjacent to a body region in a semiconductor substrate;

forming a field plate trench in a main surface of the semiconductor substrate;

forming a field electrode in the field plate trench, the field plate trench extending at the main surface and being electrically coupled to a source terminal at a plurality of positions; and

forming a contact plug for electrically coupling the field electrode to the source terminal, the contact plug comprising a contact material having a resistivity in a range from 10⁵ to 10<sup>−

1</sup> Ohm cm.

10. The method of claim 9, wherein the field electrode comprises a field plate material having a resistivity less than 1E-1 Ohm cm.

11. The method of claim 10, wherein the field plate material comprises a metal or doped polysilicon having a doping concentration of more than 1E20 cm⁻

3.

12. The method of claim 9, further comprising:

forming a source region adjacent to the main surface; and

forming a drain region adjacent to a back side surface of the semiconductor substrate opposite the main surface.

13. The method of claim 9, wherein the gate electrode is disposed in a gate trench and the gate trench and the field plate trench are merged so as to form a single trench.

14. The method of claim 9, wherein the contact material is selected from the group consisting of:

polysilicon doped at a doping concentration between 1E16 cm<sup>−

3</sup> and 1E19 cm<sup>−

3</sup>, semi-insulating polysilicon (SIPOS); and

amorphous silicon carbide.

15. The method of claim 9, further comprising:

forming a gate trench in the main surface of the semiconductor substrate,

wherein the gate electrode is disposed in the gate trench.

16. The method of claim 9, wherein the gate electrode is a planar gate electrode disposed over the main surface of the semiconductor substrate.

17. A method of manufacturing a semiconductor device, the method comprising:

forming a gate electrode adjacent to a body region in a semiconductor substrate;

forming a field plate trench in a main surface of the semiconductor substrate, the field plate trench having an extension length in a first direction,

forming a field electrode in the field plate trench, the extension length of the field plate trench in the first direction being less than double an extension length of the field plate trench in a second direction parallel to the main surface and perpendicular to the first direction, the extension length in the first direction being more than half of the extension length in the second direction; and

forming a contact plug for electrically coupling the field electrode to a terminal, the contact plug comprising a contact material having a resistivity between 10⁵ to 10<sup>−

1</sup> Ohm cm.

18. The method of claim 17, wherein the contact material is selected from the group consisting of:

polysilicon doped at a doping concentration between 1E16 cm<sup>−

3</sup> ad 1E19 cm<sup>−

3</sup>, semi-insulating polysilicon (SIPOS); and

amorphous silicon carbide.

19. The method of claim 17, further comprising:

forming a gate trench in the main surface of the semiconductor substrate,

wherein the gate electrode is disposed in the gate trench.

20. The method of claim 17, wherein the gate electrode is a planar gate electrode disposed over the main surface of the semiconductor substrate.