Semiconductor device and method for manufacturing the same

• US 9,728,651 B2
• Filed: 06/09/2016
• Issued: 08/08/2017
• Est. Priority Date: 12/18/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koezuka, Junichi
• Primary Examiner(s): Nicely, Joseph C
• Application Number:
  US15/177,480
• Publication Number:
  US 20160293767A1
• Time in Patent Office: 425 Days
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/425 producing ion implantation
• CPC Class Codes: H01L 21/426 using masks
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A transistor including an oxide semiconductor, which has good on-state characteristics, and a high-performance semiconductor device including a transistor capable of high-speed response and high-speed operation. In the transistor including an oxide semiconductor, oxygen-defect-inducing factors are introduced (added) into an oxide semiconductor layer, whereby the resistance of a source and drain regions are selectively reduced. Oxygen-defect-inducing factors are introduced into the oxide semiconductor layer, whereby oxygen defects serving as donors can be effectively formed in the oxide semiconductor layer. The introduced oxygen-defect-inducing factors are one or more selected from titanium, tungsten, and molybdenum, and are introduced by an ion implantation method.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer over an insulating surface;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode layer over the gate insulating layer; and

a source electrode layer and a drain electrode layer over the oxide semiconductor layer,

wherein the oxide semiconductor layer comprises a channel formation region, a first region, and a second region,

wherein the first region is electrically connected to the source electrode layer,

wherein the second region is electrically connected to the drain electrode layer,

wherein each of the first region and the second region contains more of one or more elements selected from titanium, tungsten, molybdenum, cobalt, and silicon than the channel formation region, and

wherein the oxide semiconductor layer contains indium, gallium, and zinc.

2. The semiconductor device according to claim 1, further comprising an insulating layer over the gate electrode layer.

3. A semiconductor device comprising:

an oxide semiconductor layer over an insulating surface;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode layer over the gate insulating layer; and

a source electrode layer and a drain electrode layer over the oxide semiconductor layer,

wherein the oxide semiconductor layer comprises a channel formation region, a first region, and a second region,

wherein the first region is electrically connected to the source electrode layer,

wherein the second region is electrically connected to the drain electrode layer,

wherein the oxide semiconductor layer contains indium, gallium, and zinc,

wherein each of the first region and the second region contains more of one or more elements selected from titanium, tungsten, molybdenum, cobalt, and silicon than the channel formation region, and

wherein the oxide semiconductor layer includes a region including a crystal whose c-axis is aligned in a direction within ±

10°

from a perpendicular direction to a surface of the oxide semiconductor layer.

4. The semiconductor device according to claim 3, further comprising a first insulating layer over the gate electrode layer.

5. The semiconductor device according to claim 4, further comprising a second insulating layer over the first insulating layer.

6. A semiconductor device comprising:

an oxide semiconductor layer over an insulating surface;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode layer over the gate insulating layer; and

a source electrode layer and a drain electrode layer over the oxide semiconductor layer,

wherein the oxide semiconductor layer comprises a channel formation region, a first region, and a second region,

wherein the first region is electrically connected to the source electrode layer,

wherein the second region is electrically connected to the drain electrode layer,

wherein the oxide semiconductor layer contains indium, gallium, and zinc,

wherein each of the first region and the second region contains more of one or more elements selected from titanium, tungsten, molybdenum, cobalt, and silicon than the channel formation region,

wherein the oxide semiconductor layer includes a region including a crystal whose c-axis is aligned in a direction within ±

10°

from a perpendicular direction to a surface of the oxide semiconductor layer, and

wherein a carrier concentration of the channel formation region is lower than 1×

10¹⁷/cm³.

7. The semiconductor device according to claim 6, further comprising a first insulating layer over the gate electrode layer.

8. The semiconductor device according to claim 7, further comprising a second insulating layer over the first insulating layer.