Resistive memory device

• US 9,728,721 B2
• Filed: 07/25/2014
• Issued: 08/08/2017
• Est. Priority Date: 07/25/2014
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Tan, Shyue Seng, Toh, Eng Huat, Tran, Xuan Anh, Sun, Yuan, Quek, Elgin Kiok Boone
• Primary Examiner(s): Ahmadi, Mohsen
• Assistant Examiner(s): SPALLA, DAVID C
• Application Number:
  US14/340,582
• Publication Number:
  US 20160028009A1
• Time in Patent Office: 1,110 Days
• Field of Search: 257 1- 5
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/821 Device geometry
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A non-volatile memory device and a manufacturing method thereof are provided. The memory device includes a substrate, a lower cell dielectric layer with gate conductors and a body unit conductor disposed on the lower cell dielectric layer and gates. Memory element conductors are disposed on the body unit and lower cell dielectric layer. An upper cell dielectric layer may be on the substrate and over the lower cell dielectric layer, body unit conductor and memory element conductors. The upper cell dielectric layer isolates the memory element conductors.

Claims

1. A method for forming a device comprising:

providing a substrate prepared with a lower cell dielectric layer with gate conductors disposed in a first direction, wherein the gate conductors are elongated gate conductors formed in the lower cell dielectric layer and separated by the lower cell dielectric layer;

forming a body unit conductor over a top surface of the lower cell dielectric layer and gate conductors, wherein the body unit conductor is disposed in and along a second direction orthogonal to the first direction and traverses the gate conductors;

forming memory element conductors on the body unit conductor and lower cell dielectric layer, wherein the memory element conductors are elongated memory element conductors disposed in and along the same first direction over the gate conductors; and

forming an upper cell dielectric layer on the substrate to cover the lower cell dielectric layer, body unit conductor and memory element conductors, wherein the upper cell dielectric layer isolates the memory element conductors from each other.

2. The method of claim 1 wherein the gate conductors have a planar surface with the lower cell dielectric layer.

3. The method of claim 1 wherein:

the gate conductors have a top surface disposed over a top surface of the lower cell dielectric layer, creating gate conductor mesas;

the body unit conductor is disposed on the gate conductor mesas, creating body mesas; and

forming memory element conductors on the body mesas.

4. The method of claim 1 wherein:

the gate conductors have a top surface disposed below a top surface of the lower cell dielectric layer, creating gate conductor recesses;

the body unit conductor is disposed on the lower cell dielectric layer and lines the gate conductor recesses, creating body recesses; and

the memory element conductors are disposed in the body recesses.

5. The method of claim 1 wherein the memory element conductors comprise resistive memory element conductors.

6. The method of claim 5 wherein the resistive memory element conductors comprise phase change memory element conductors.

7. The method of claim 5 wherein the memory element conductors comprise non-thermal resistive memory element conductors.

8. The method of claim 1 wherein the body unit conductor comprises:

a gate dielectric layer; and

a body layer to serve as bodies of transistors of a column of memory cells.

9. The method of claim 8 wherein:

the gate dielectric layer serves as a common gate dielectric layer of columns of memory cells; and

the body layer comprises silicon.

10. The method of claim 1 wherein:

the body unit conductor comprises a transistor body layer and a gate dielectric layer, wherein first and second source/drain (S/D) regions and channel regions of cell select transistors are disposed in the transistor body layer; and

each of the memory element conductors comprises first and second storage terminals, wherein the first S/D region of a cell select transistor is coupled to and in direct contact with the first storage terminal while the second S/D region of the cell select transistor is coupled to and in direct contact with the second storage terminal of the memory element conductor.

11. The method of claim 1 comprising:

patterning the lower cell dielectric layer to form trenches, wherein the trenches are elongated trenches disposed along the first direction and the trenches extend from the top surface of the lower cell dielectric layer and partially into the lower cell dielectric layer such that bottom of the trenches is above a bottom surface of the lower cell dielectric layer;

forming a gate electrode layer over the substrate and fills the trenches; and

removing excess gate electrode layer, leaving the gate conductors in the trenches.

12. The method of claim 1 wherein forming the body unit conductor on the lower cell dielectric layer and gate conductors comprises:

forming body unit layers which comprise a gate dielectric layer and a body layer over the lower cell dielectric layer; and

patterning the body unit layers to form the body unit conductor which is an elongated member disposed in and along the second direction and traverses the gate conductors.

13. The method of claim 12 wherein forming the memory element conductors comprises:

depositing a storage element layer on the substrate, covering the lower cell dielectric layer and body unit conductor; and

patterning the storage element layer to form the elongated memory element conductors disposed in and along the same first direction.

14. The method of claim 13 wherein patterning the storage element layer forms the elongated memory element conductors that have a width which is wider than a width of the elongated gate conductors.

15. The method of claim 13 comprising forming first and second source/drain (S/D) regions in the body layer by ion implantation, wherein the S/D regions are formed adjacent to sides of the gate conductors and the memory element conductors, and wherein the implantation is self-aligned to the memory element conductors.

16. The method of claim 15 wherein:

the gate conductor and S/D regions formed in the body layer adjacent to first and second sides of the gate conductor correspond to a cell select transistor of a memory cell;

the memory element conductor corresponds to a storage unit of the memory cell.

17. The method of claim 16 comprising coupling a column of memory cells disposed along the second direction in between first and second column selectors, wherein the first and second column selectors comprise the same structure as the memory cell.

18. A method for forming a device comprising:

providing a substrate prepared with a lower cell dielectric layer with first type conductors disposed in and extends along a first direction, wherein the first type conductors are elongated first type conductors separated by the lower cell dielectric layer;

forming a body unit conductor over a top surface of the lower cell dielectric layer and first type conductors, wherein the body unit conductor is disposed in and extends along a second direction orthogonal to the first direction and traverses the first type conductors;

forming second type conductors on the body unit conductor and the lower cell dielectric layer, wherein the second type conductors are elongated second type conductors disposed in and extend along a direction which is parallel to the first direction over the first type conductors, wherein the first and second type conductors directly contact the body unit conductor; and

forming an upper cell dielectric layer on the substrate to cover the lower cell dielectric layer, body unit conductor and second type conductors, wherein the upper cell dielectric layer isolates the second type conductors from each other.

19. The method of claim 18 wherein:

the first type conductors have a top surface which is coplanar with the top surface of the lower cell dielectric layer; and

the upper cell dielectric layer comprises voids formed in between adjacent second type conductors.

20. The method of claim 18 wherein:

the first type conductors have a top surface disposed over a top surface of the lower cell dielectric layer, creating first type conductor mesas;

the body unit conductor is disposed on the gate conductor mesas, creating body mesas; and

forming second type conductors on the body mesas.

21. The method of claim 18 wherein:

the first type conductors have a top surface disposed below a top surface of the lower cell dielectric layer, creating first type conductor recesses;

the body unit conductor is disposed on the lower cell dielectric layer and lines the first type conductor recesses, creating body recesses; and

the second type conductors are disposed in the body recesses.

22. A method for forming a device comprising:

providing a substrate prepared with a lower cell dielectric layer with first type conductors disposed in and extends along a first direction, wherein the first type conductors are elongated first type conductors separated by the lower cell dielectric layer, wherein the first type conductors comprise gate conductors;

forming a body unit conductor over a top surface of the lower cell dielectric layer and first type conductors, wherein the body unit conductor is disposed in and extends along a second direction orthogonal to the first direction and traverses the first type conductors;

forming second type conductors on the body unit conductor and the lower cell dielectric layer, wherein the second type conductors are elongated second type conductors disposed in and extend along a direction which is parallel to the first direction over the first type conductors, wherein the second type conductors comprise memory element conductors; and

forming an upper cell dielectric layer on the substrate to cover the lower cell dielectric layer, body unit conductor and second type conductors, wherein the upper cell dielectric layer isolates the second type conductors from each other.