Isolation module for use between power rails in an integrated circuit

• US 9,729,151 B2
• Filed: 10/04/2013
• Issued: 08/08/2017
• Est. Priority Date: 10/04/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Tan, Fern Nee, Soman, Sanjiv, Levin, Alexander, Rajagopalan, Srinivasan
• Primary Examiner(s): Fureman, Jared
• Assistant Examiner(s): Warmflash, Michael
• Application Number:
  US14/046,592
• Publication Number:
  US 20150097431A1
• Time in Patent Office: 1,404 Days
• Field of Search: 307 72
• CPC Class Codes: H01L 2223/6688 Mixed frequency adaptations, i.e. for operation at different frequencies
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H03K 19/00346 Modifications for eliminating interference or parasitic voltages or currents

Abstract

An integrated circuit (IC) can include multiple power domains that are served by a common power source. In an example, a first IC power rail can be coupled to the source and a first consumer circuit. A second IC power rail can be coupled to a second consumer circuit. The second IC power rail can receive a filtered power signal from an isolation module that is coupled between the first and second power rails. In an example, an isolation module includes an integrated inductor and a capacitor (e.g., a land-side capacitor). The integrated inductor can optionally include multiple spaced apart conductive layers that are electrically coupled. The integrated inductor can optionally include a series of conductive traces and plated through holes or vias that together provide a current path with multiple turns.

Claims

1. An integrated circuit package comprising:

a first power rail coupled to a power supply node, the first power rail configured to transmit a first power signal from the power supply node to a first consumer circuit;

a second power rail configured to transmit a second power signal, based on the first power signal, to a different second consumer circuit; and

a first isolation module configured to receive the first power signal from the first power rail and, in response, provide the second power signal at the second power rail, the first isolation module comprising a first integrated inductor and a first integrated capacitor;

wherein the first integrated inductor includes first and second inductor terminals coupled respectively to the first and second power rails; and

wherein the first integrated capacitor includes a first capacitor terminal coupled to the first power rail, and a second capacitor terminal coupled to a reference ground node.

2. The integrated circuit package of claim 1, wherein the first and second consumer circuits are operable at different switching frequencies.

3. The integrated circuit package of claim 1, comprising:

a third power rail configured to transmit a third power signal, based on the second power signal, to a third consumer circuit; and

a second isolation module configured to receive the second power signal from the second power rail and, in response, provide the third power signal at the third power rail, the second module comprising a second integrated inductor and a second integrated capacitor.

4. The integrated circuit package of claim 1, wherein the first integrated inductor comprises:

a first trace in a first layer, a second trace in a second layer, the second layer spaced apart from and parallel to the first layer; and

a via that electrically couples the first and second traces.

5. The integrated circuit package of claim 4, wherein the first and second traces are overlapping and each of the first and second traces comprises multiple turns.

6. The integrated circuit package of claim 4, wherein the first and second traces are rectangular and spiral shaped, and the first and second traces each comprise at least three turns each.

7. The integrated circuit package of claim 4, wherein the first integrated inductor has an inductance of about 4 nH.

8. The integrated circuit package of claim 4, wherein the first integrated inductor has a centrally-located void volume.

9. The integrated circuit package of claim 8, wherein the first integrated inductor occupies a landing area of about 1 mm square, and wherein a cross-sectional area of the void volume occupies less than about 20% of the 1 mm square landing area.

10. The integrated circuit package of claim 1, wherein the first integrated inductor comprises multiple spaced apart vias that are coupled in series.

11. The integrated circuit package of claim 1, wherein the first integrated inductor comprises spaced apart first and second vias corresponding respectively to the first and second terminals of the first integrated inductor;

wherein the first via is electrically coupled to different first and second conductive planar traces;

wherein the second via is electrically coupled to the second conductive planar trace and to a different third conductive planar trace;

wherein the second via is electrically coupled to the first via using the second trace to form at least a portion of an inductor turn; and

wherein the first, second, and third traces are parallel.

12. The integrated circuit package of claim 11, wherein the first integrated inductor comprises a third via that is electrically coupled to a fourth conductive planar trace that is parallel to the other traces, and the third via is electrically coupled to the second via using the third layer;

and

wherein the third via is disposed nearer to the first via than is the second via.

13. The integrated circuit package of claim 1, wherein the first integrated capacitor includes a land-side capacitor circuit disposed on an interconnect side of a die comprising the integrated circuit package.