Integrated device packages having a MEMS die sealed in a cavity by a processor die and method of manufacturing the same

• US 9,731,959 B2
• Filed: 11/26/2014
• Issued: 08/15/2017
• Est. Priority Date: 09/25/2014
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Saiyed, Shafi, Sengupta, Dipak
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): Boulghassoul, Younes
• Application Number:
  US14/554,661
• Publication Number:
  US 20160090298A1
• Time in Patent Office: 993 Days
• CPC Class Codes: B81B 7/0048 between the MEMS die and the substrate
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

An integrated device package is disclosed. The package includes a substrate comprising a cavity through a top surface of the substrate. A first integrated device die is positioned in the cavity. The first integrated device die includes one or more active components. A second integrated device die is attached to the top surface of the substrate and positioned over the cavity. The second integrated device die covers the cavity. Encapsulant can cover the second integrate device die.

Claims

1. An integrated device package comprising:

a package substrate comprising a cavity through a top surface of the package substrate;

a first integrated device die positioned in the cavity, the first integrated device die comprising a microelectromechanical systems (MEMS) die having one or more active components, the first integrated device die electrically connected to one or more conductive lands disposed in the cavity;

a second integrated device die attached to the top surface of the package substrate and positioned over the cavity, the second integrated device die comprising a processor die in electrical communication with the MEMS die, the second integrated device die covering the cavity and sealing the cavity from outside environs; and

a ledge recessed from the top surface of the package substrate, the ledge comprising the one or more conductive lands, wherein the first integrated device die is electrically connected to the one or more conductive lands of the ledge.

2. The package of claim 1, further comprising an encapsulant over the second integrated device die and portions of the top surface of the package substrate.

3. The package of claim 2, wherein the cavity comprises air or a vacuum.

4. The package of claim 2, wherein the encapsulant is not disposed in the cavity.

5. The package of claim 1, wherein the first integrated device die is electrically connected to the package substrate.

6. The package of claim 5, wherein the first integrated device die is wire bonded to the one or more conductive lands of the ledge.

7. The package of claim 1, wherein the processor die is grounded to shield the MEMS die.

8. The package of claim 1, wherein the package substrate comprises a base portion and a wall extending transverse to the base portion, the wall formed with or attached to the base portion, the cavity defined at least in part by the base portion and the wall.

9. The package of claim 8, wherein the package substrate comprises a printed circuit board, the cavity comprising a recess in the printed circuit board.

10. The package of claim 1, further comprising a cap over the MEMS die, wherein the entire cap and the entire MEMS die are disposed within the cavity.

11. A method for manufacturing an integrated device package, the method comprising:

providing a package substrate comprising a cavity through a top surface of the package substrate, the package substrate comprising a ledge recessed from the top surface of the package substrate, the ledge comprising one or more conductive lands;

positioning a first integrated device die in the cavity, the first integrated device die comprising a microelectromechanical systems (MEMS) die having one or more active components;

electrically connecting the first integrated device die with the one or more conductive lands of the ledge disposed in the cavity;

positioning a second integrated device die over the cavity; and

attaching the second integrated device die to the top surface of the package substrate to cover the cavity and to seal the cavity from outside environs,

wherein the second integrated device die comprises a processor die in electrical communication with the MEMS die.

12. The method of claim 11, further comprising applying an encapsulant over the second integrated device die and portions of the top surface of the package substrate.

13. The method of claim 11, further comprising forming the ledge to be recessed from the top surface of the package substrate.

14. The method of claim 13, wherein electrically connecting the first integrated device die comprises wire bonding the first integrated device die to the one or more conductive lands of the ledge.

15. The method of claim 11, further comprising forming the cavity.

16. An integrated device package comprising:

a package substrate comprising a cavity;

a first integrated device die disposed in the cavity, the first integrated device die comprising a microelectromechanical systems (MEMS) die, the first integrated device die electrically connected to one or more conductive lands disposed in the cavity;

an encapsulant over at least a portion of a top surface of the package substrate;

a ledge recessed from the top surface of the package substrate, the ledge comprising the one or more conductive lands, wherein the first integrated device die is electrically connected to the one or more conductive lands of the ledge; and

a component that seals the cavity, wherein the component that seals the cavity comprises a processor die in electrical communication with the MEMS die, and

wherein the encapsulant does not contact at least an active side of the first integrated device die, and wherein the cavity and the first integrated device die are sealed from outside environs and the encapsulant.

17. The package of claim 16, wherein the processor die is attached to the top surface of the package substrate to seal the cavity.

18. The package of claim 16, wherein the first integrated device die is wire bonded to the one or more conductive lands of the ledge.