MEMS-CMOS-MEMS platform

• US 9,731,961 B2
• Filed: 07/10/2015
• Issued: 08/15/2017
• Est. Priority Date: 07/10/2015
• Status: Active Grant

• Current Assignee: Invensense Incorporated (TDK Corporation)
• Original Assignee: Invensense Incorporated (TDK Corporation)
• Inventors: Lloyd, Stephen, Gurin, Ilya
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): WITHERS, GRANT S
• Application Number:
  US14/797,013
• Publication Number:
  US 20170008760A1
• Time in Patent Office: 767 Days
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 7/0054 between other parts not provided for in B81B7/0048 - B81B7/0051
• CPC Class Codes: B81B 7/0074 3D packaging, i.e. encapsulation containing one or several MEMS devices arranged in planes non-parallel to the mounting board
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A package combining a MEMS substrate, a CMOS substrate and another MEMS substrate in one package that is vertically stacked is disclosed. The package comprises a sensor chip further comprising a first MEMS substrate and a CMOS substrate with a first surface and a second surface and where the first MEMS substrate is attached to the first surface of the CMOS substrate. The package further includes a second MEMS substrate with a first surface and a second surface, where the first surface of the second MEMS substrate is attached to the second surface of the CMOS substrate and the second surface of the second MEMS substrate is attached to a packaging substrate. The first MEMS substrate, the CMOS substrate, the second MEMS substrate and the packaging substrate are provided with electrical inter-connects.

Claims

1. A package comprising:

a sensor chip comprising;

a first MEMS substrate;

a CMOS substrate with a first surface and a second surface, wherein the first MEMS substrate is attached to the first surface of the CMOS substrate, and

a second MEMS substrate with a first surface and a second surface;

wherein the first surface of the second MEMS substrate is attached to the second surface of the CMOS substrate and the second surface of the second MEMS substrate is attached to a packaging substrate, the second MEMS substrate comprising a first cavity within the first surface of the second MEMS substrate and a second cavity within the second surface of the second MEMS substrate;

wherein the first MEMS substrate, the CMOS substrate, the second MEMS substrate and the packaging substrate are connected through electrical interconnects.

2. The package of claim 1, wherein the second MEMS substrate further comprises a handle substrate and an attached device layer.

3. The package of claim 2, wherein the device layer comprises a moveable structure.

4. The package of claim 1, wherein the first MEMS substrate further comprises a cavity.

5. The package of claim 4, wherein the cavity is a recess on a surface attached to the CMOS substrate.

6. The package of claim 5, wherein the cavity of the first MEMS substrate is configured to receive a MEMS sensor and to provide stress isolation between the CMOS substrate and the first MEMS substrate.

7. The package of claim 1, wherein the first MEMS substrate further comprises a handle substrate and an attached device layer.

8. The package of claim 7, wherein the device layer comprises a moveable structure.

9. The package of claim 1, wherein the CMOS substrate further comprises an interconnect layer on the first surface.

10. The package of claim 9, wherein the interconnect layer comprises any of electrically conductive metal and semiconductor material.

11. The package of claim 1, wherein the CMOS substrate further comprises an electrical interconnect layer on the second surface.

12. The package of claim 11, wherein the electrical interconnect layer comprises any of electrically conductive metal and semiconductor material.

13. The package of claim 1, wherein the electrical interconnects further comprise any one of through-silicon via, solder bond, eutectic bond, wire bond and a combination thereof.

14. The package of claim 1, wherein the first MEMS substrate and the CMOS substrate, the CMOS substrate and the second MEMS substrate, and the second MEMS substrate and the packaging substrate are attached through a mechanical connection.

15. The package of claim 14 wherein the mechanical connection further comprises any of eutectic bonding, fusion bonding, solder bonding, low stress adhesive material and a combination thereof.

16. The package of claim 1, wherein the second MEMS substrate further comprises any of a blank substrate, a patterned non-active silicon substrate, a substrate containing a MEMS structure and a combination thereof.

17. The package of claim 1, wherein the second MEMS substrate comprises CMOS circuits.

18. The package of claim 1, wherein the first cavity is configured to receive a MEMS sensor and to provide stress isolation between the CMOS substrate and the second MEMS substrate.

19. The package of claim 18, wherein the second MEMS substrate further comprises a third cavity within the first surface of the second MEMS substrate, wherein the third cavity is configured to receive a second MEMS sensor and to provide stress isolation between the CMOS substrate and the second MEMS substrate.

20. The package of claim 1, wherein the second cavity is configured to provide stress isolation between the packaging substrate and the second MEMS substrate.

21. The package of claim 20, wherein the second MEMS substrate further comprises a third cavity within the second surface of the second MEMS substrate, wherein the third cavity is configured to provide stress isolation between the packaging substrate and the second MEMS substrate.