Current balancing, current sensor, and phase balancing apparatus and method for a voltage regulator

• US 9,733,282 B2
• Filed: 11/17/2014
• Issued: 08/15/2017
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lyakhov, Alexander, Tang, Chiu Keung, Raghuraman, Narayanan, Natarajan, Narayanan, Schrom, Gerhard, Hodgson, J. Keith
• Primary Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US14/543,346
• Publication Number:
  US 20150069995A1
• Time in Patent Office: 1,002 Days
• Field of Search: 341144
• CPC Class Codes: G01R 19/0092 measuring current only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G06T 3/40 Scaling of whole images or parts thereof, e.g. expanding or contracting
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/1566 with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H03L 5/00 Automatic control of voltage, current, or power
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/685 the quantisation value generators of both converters being arranged in a common two-dimensional array

Abstract

Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. are provided here. An apparatus is provided which comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

Claims

1. An apparatus comprising:

a plurality of inductors at least one of which is coupled to a capacitor and a load;

a plurality of bridges at least one of which is coupled to the at least one inductor from the plurality of inductors; and

a plurality of current sensors at least one of which is coupled to the at least one bridge to sense current through a transistor of the at least one bridge, wherein the at least one bridge includes a high-side switch and a low-side switch, wherein the high-side switch includes two transistors coupled in series, and wherein the low-side switch includes two transistors coupled in series.

2. The apparatus of claim 1 further comprises a circuit to generate an average current using sensed current from at least one of the current sensors of the plurality of current sensors.

3. The apparatus of claim 2 further comprises an over-current protection circuit to receive the average current and to generate an over-current protection signal according to the average current.

4. The apparatus of claim 2 further comprises a power control unit (PCU) to receive the average current.

5. The apparatus of claim 1, wherein the at least one current sensor comprises:

a first current sensor for sensing current through the high-side switch of the at least one bridge; and

a second current sensor for sensing current through the low-side switch of the at least one bridge.

6. The apparatus of claim 5, wherein the first and second current sensors include a common gate amplifier.

7. The apparatus of claim 5, wherein the first and the second current sensors are to generate a corresponding differential current output.

8. The apparatus of claim 7 further comprises a circuit to convert the corresponding differential current output to a corresponding single-ended current output.

9. The apparatus of claim 5, wherein the first current sensor is coupled to the second current sensor to generate a combined differential current output.

10. The apparatus of claim 9 further comprises a circuit to convert the combined differential current output to a single ended current output.

11. An apparatus comprising:

a first current sensor for sensing current through a high-side switch;

a second current sensor for sensing current through a low-side switch, wherein the low-side switch is coupled to the high-side bridge, wherein the high-side switch includes two transistors coupled in series, and wherein the low-side switch includes two transistors coupled in series; and

a circuit to generate an average current using sensed current from the first and second current sensors.

12. The apparatus of claim 11 comprises an over-current protection circuit to receive the average current and to generate an over-current protection signal according to the average current.

13. The apparatus of claim 12 comprises a telemetry circuit for receiving output from the current sensor receiver.

14. The apparatus of claim 11 comprises a current sensor receiver to receive outputs from both the first and second current sensors, wherein the current sensor receiver is to operate on a power supply having a voltage level lower than voltage level of a power supply for the first and second sensors.

15. The apparatus of claim 11, wherein the first sensor is coupled in parallel to at least part of the high-side switch, and wherein the second sensor is coupled in parallel to at least part of the low-side switch.

16. The apparatus of claim 11 comprises:

a first current receiver to receive an output from the first current sensor; and

a second current receiver to receive an output from the second current sensor, wherein the circuit is to use outputs of the first and second current receivers to generate the average current.

17. A system comprising:

a memory;

a processor coupled to the memory, the processor comprising;

a first current sensor for sensing current through a high-side switch;

a second current sensor for sensing current through a low-side switch, wherein the low-side switch is coupled to the high-side bridge, wherein the high-side switch includes two transistors coupled in series, and wherein the low-side switch includes two transistors coupled in series; and

a circuit to generate an average current using sensed current from the first and second current sensors, wherein the high-side and low-side switches are part of a voltage regulator; and

a wireless interface for allowing the processor to communicate with another device.

18. The system of claim 17, wherein the memory is one of a volatile or non-volatile memory.

19. The system of claim 17, wherein the processor comprises a telemetry circuit for receiving average current and for providing a mechanism for monitoring the average current.

20. The system of claim 17, wherein the processor comprises a power control unit (PCU) to receive the average current.

21. An apparatus comprising:

a plurality of bridges at least one of which is to be coupled to at least one inductor from a plurality of inductors; and

a plurality of current sensors at least one of which is coupled to the at least one bridge to sense current through a transistor of the at least one bridge, wherein the at least one bridge includes a high-side switch, and wherein the high-side switch includes two transistors coupled in series.

22. The apparatus of claim 21 further comprises a circuit to generate an average current using sensed current from at least one of the current sensors of the plurality of current sensors.

23. The apparatus of claim 21 comprises:

a wave generator to generate a plurality of wave signals;

a plurality of comparators to generate a plurality of phase width modulated (PWM) signals; and

a plurality of resistors at least one of which is coupled to a comparator of the plurality of comparators, and coupled to the wave generator.

24. The apparatus of claim 23, wherein at least one resistor of the plurality of resistors is to generate an error current from a difference of the average current and a corresponding sensed current of the at least one bridge.