Tap, CMD with two flip-flops, routing circuit, and data register

• US 9,733,308 B2
• Filed: 10/27/2016
• Issued: 08/15/2017
• Est. Priority Date: 07/29/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US15/336,101
• Publication Number:
  US 20170045580A1
• Time in Patent Office: 292 Days
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H10K 2102/00 Constructional details relating to the organic devices covered by this subclass
• CPC Class Codes: H10K 2102/103 comprising indium oxides, e.g. ITO
• CPC Class Codes: H10K 50/814 combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
• CPC Class Codes: H10K 50/816 Multilayers, e.g. transparent multilayers
• CPC Class Codes: H10K 50/844 Encapsulations
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/122 Pixel-defining structures or layers, e.g. banks
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass

Abstract

This disclosure describes different ways to improve the operation of a device'"'"'s 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP'"'"'s Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a third embodiment of the disclosure the at-speed operations are achieved by detecting the TAP'"'"'s Exit1DR and PauseDR states and in response producing Capture and Update signals that are input to a Programmable Switch that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a fourth embodiment of the disclosure the at-speed operations are achieved by detecting the TAP'"'"'s Exit1DR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. Each of the embodiments may be augmented to include externally accessible Update and Capture input signals that can be selected to allow a tester to directly control the at-speed operations of a circuit. The improvements of the disclosure are achieved without requiring any additional IC pins beyond the 4 required TAP pins, except for examples showing use of additional data input pins (TDI or WPI signals), additional data output pins (TDO or WPO signals) or examples showing use of additional control input pins (Capture and Update signals). Devices including the TAP improvements can be operated compliantly in a daisy-chain arrangement with devices that don'"'"'t include the TAP improvements.

Claims

1. An integrated circuit comprising:

(a) a TDI signal lead, a TDO signal lead, a TCK signal lead and a TMS signal lead;

(b) a TAP state machine having an input coupled to the TCK signal lead, an input coupled to the TMS signal lead, instruction register control outputs, and data register control outputs;

(c) an instruction register having an input coupled to the TDI signal lead, an output coupled to the TDO signal lead, control inputs coupled to the instruction control outputs of the TAP state machine and enable outputs;

(d) a commandable data register control router including;

(i) a command circuit having a first flip flop with;

an inverted clock input connected to the TCK signal lead;

a data input connected to the TMS signal lead;

a reset input connected to the data register control outputs; and

a first control output; and

a second flip flop with;

an inverted clock input connected to the TCK signal lead;

a data input connected to the first control output of the first flip flop;

a reset input connected to the data register control outputs; and

a second control output; and

(ii) a routing circuit having first control inputs coupled to the data register control outputs of the TAP state machine, second control inputs coupled to the first and second control outputs of the command circuit, data register control outputs and enable inputs coupled to the enable outputs of the instruction register; and

(e) a data register having an input coupled to the TDI signal lead, an output coupled to the TDO signal lead, and control inputs coupled to the data register control outputs of the routing circuit.

2. The integrated circuit of claim 1 including functional circuitry and the data register is coupled to the functional circuitry.

3. The integrated circuit of claim 1 including functional circuitry and the data register is a debug register coupled to the functional circuitry.

4. The integrated circuit of claim 1 including functional circuitry and the data register is a programming data register coupled to the functional circuitry.

5. The integrated circuit of claim 1 including instrumentation circuitry and the data register is an instrumentation data register coupled to the instrumentation circuitry.

6. The integrated circuit of claim 1 including functional circuitry having interconnects and the data register is a boundary register coupled to the interconnects and the functional circuitry.

7. The integrated circuit of claim 1 including functional circuitry and the data register is a boundary register coupled to the functional circuitry.

8. The integrated circuit of claim 1 including core circuitry having core interconnects and the data register is a core wrapper boundary register coupled to the core interconnects circuitry.

9. The integrated circuit of claim 1 including core system logic and the data register is a core wrapper boundary register coupled to the core system logic.

10. The integrated circuit of claim 1 including functional circuitry having interconnects and another integrated circuit having interconnects and the data register is a boundary register coupled to the interconnects of the functional circuitry and the other integrated circuit.

11. The integrated circuit of claim 1 including first core circuitry and second core circuitry separate from the integrated circuit and the data register is a core wrapper boundary register coupled between the two cores.

12. The integrated circuit of claim 1 including first core circuitry and second core circuitry separate from the integrated circuit, the first core circuitry and the second core circuitry being coupled together and the data register is a boundary register coupled between the first core circuitry and the second core circuitry.

13. The integrated circuit of claim 1 in which the data register control outputs include a SHIFT output connected to the reset inputs of the flip flops.