Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

• US 9,733,831 B2
• Filed: 07/01/2014
• Issued: 08/15/2017
• Est. Priority Date: 11/13/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Ohmacht, Martin
• Primary Examiner(s): Yi, David X
• Assistant Examiner(s): GOLDSCHMIDT, CRAIG S
• Application Number:
  US14/320,841
• Publication Number:
  US 20150006840A1
• Time in Patent Office: 1,141 Days
• Field of Search: None
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0671 In-line storage system
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/522 Barrier synchronisation
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

Claims

1. A method for memory synchronization for use in a multiprocessor system having a plurality of processors and a memory device coupled to the processors, the method comprising:

receiving, at a memory unit associated with a processor, one or more memory access requests from one or more processors;

broadcasting a central generation indication from a memory synchronization unit; and

at each memory unit;

tagging each memory access request with bits representing a global generation number responsive to the central generation indication;

OR-ing said tagged bits from each memory access request to determine what generations are in flight and generating a vector representing generations in flight; and

supplying said generated vector to a global OR reduce tree; and

aggregating, at said global OR reduce tree, information from said generated vectors from each said memory unit about current generations of memory requests in flight; and

delaying memory access requests responsive to said information aggregated at said global OR reduce tree.

2. The method of claim 1, wherein

the central generation indication comprises a pointer value and

the operations comprise,

holding incrementation of the pointer value so long as a given generation is in flight;

and

when given generations in flight are completed, incrementing the pointer value.

3. The method of claim 1, wherein the central indication comprises a first count indicating a generation and a second count indicating a reclaim pointer.

4. The method of claim 3, comprising preventing the first and second count from passing each other.

5. A central memory synchronization module for use in a multiprocessor system, the system comprising a plurality of processors and a memory device coupled to the processors, the module comprising

at least one global generation bit counter configured to issue a global numeric generation indication;

a plurality of memory units, each memory unit configured to;

receive and store memory access requests from said processors;

tag each memory access request with bits representing a global generation number responsive to the global numeric generation indication;

apply OR-ing logic to said tagged bits from each memory access request to determine what generations are in flight and generate a vector representing generations in flight for the memory unit; and

supplying said generated vector from each memory unit to

at least one global OR reduce tree, said global OR reduce tree for aggregating information from said generated vectors from each said memory unit about current generations of memory requests in flight; and

at least one broadcast facility for broadcasting the generation indication and a result derived from the OR reduce tree.

6. The module of claim 5,

wherein the global generation

bit counter defines a current generation of memory access;

said module further comprising;

a reclaim pointer for pointing to an oldest generation in flight; and

said module further comprising;

at least one broadcast interface for providing a value of the counter and the reclaim pointer to the system; and

a request interface for coupling within the system and receiving synchronization requests.

7. The module of claim 5, wherein the at least one global OR reduce tree is configured to:

receive a plurality of respective vectors—

each respective vector having a respective bit for each possible generation, indicating whether there are memory accesses in flight for that generation—

from each unit capable of requesting memory access; and

apply OR-ing logic to the respective vectors to determine whether there are memory access requests in flight for any generation.

8. The module of claim 5, wherein the multiprocessor system further comprises:

at least one synchronization controller unit configured to couple with a synchronization requesting processor and an OR reduce tree end-point, and a plurality of respective generation detectors for tracking a current generation associated with a requesting processor.