Write buffering

• US 9,734,067 B1
• Filed: 04/16/2015
• Issued: 08/15/2017
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Dela Cruz, Elmer Paule, Arcedera, Mark Ian Alcid, Bruce, Rolando H.
• Primary Examiner(s): Oberly, Eric
• Application Number:
  US14/689,045
• Time in Patent Office: 852 Days
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0844 Multiple simultaneous or quasi-simultaneous cache accessing
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/217 Hybrid disk, e.g. using both magnetic and solid state storage devices
• CPC Class Codes: G06F 2212/225 Hybrid cache memory, e.g. having both volatile and non-volatile portions
• CPC Class Codes: G06F 2212/313 In storage device
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower. Methods provided here may be extended for systems that have more than two cache levels.

Claims

1. An apparatus for storing data, comprising:

a hybrid storage device comprising;

an SRAM memory (static random access memory) configured to buffer write data from a host;

a non-volatile memory;

an SDRAM memory (synchronous dynamic random access memory) configured to communicate with a hard disk drive;

a DMA (direct memory access) controller configured to transfer data between the hard disk drive and the SRAM memory;

a flash interface controller configured to transfer data between the SRAM memory and the non-volatile memory;

wherein the hybrid storage device provides a write buffering scheme comprising the SRAM memory, the non-volatile memory and the SDRAM memory,

wherein, if the non-volatile memory is not full, then the flash interface controller copies the write data from the SRAM memory to the non-volatile memory if a pre-defined threshold of unused cache lines is reached in the SRAM memory or if the write data in the SRAM memory is dirty prior to writing new write data to the SRAM memory;

wherein, if the non-volatile memory is full, then the DMA controller is configured to flush the write data from the SRAM memory to the hard disk drive if the pre-defined threshold of unused cache lines is reached in the SRAM memory or if the write data in the SRAM memory is dirty prior to writing new write data to the SRAM memory;

wherein the flash interface controller copies data from the non-volatile memory to the SDRAM memory when data is transferred from the non-volatile memory to the SDRAM memory;

wherein the non-volatile memory is slower than the SRAM memory;

wherein the non-volatile memory has a greater storage capacity than the SRAM memory;

wherein the non-volatile memory is slower than the SDRAM memory;

wherein the non-volatile memory has a greater storage capacity than the SDRAM memory; and

wherein the SDRAM memory is slower than the SRAM memory.

2. The apparatus of claim 1, wherein the non-volatile memory comprises at least one flash memory device.

3. The apparatus of claim 1, wherein the DMA controller comprises at least a first IO (input/output) interface DMA controller configured to transfer data between the SDRAM memory and the hard disk drive.

4. The apparatus of claim 3, wherein the DMA controller further comprises a second IO interface DMA controller configured to transfer data between the host and the SRAM memory.

13. The apparatus of claim 1, wherein if the write data in the SRAM memory is clean prior to writing the new write data to the SRAM memory, then the flash interface controller overwrites the write data in the SRAM memory.

5. A method for storing data comprising:

buffering, in an SRAM memory (static random access memory), write data from a host;

transferring, by a flash interface controller, data between the SRAM memory and a non-volatile memory;

wherein said transferring comprises;

if the non-volatile memory is not full, then copying, by the flash interface controller, the write data from the SRAM memory to the non-volatile memory if a pre-defined threshold of unused cache lines is reached in the SRAM memory or if the write data in the SRAM memory is dirty prior to writing new write data to the SRAM memory;

if the non-volatile memory is full, then a DMA (Direct Memory Access) controller is configured to flush the write data from the SRAM memory to a hard disk drive if the pre-defined threshold of unused cache lines is reached in the SRAM memory or if the write data in the SRAM memory is dirty prior to writing new write data to the SRAM memory;

wherein the flash interface controller copies data from the non-volatile memory to an SDRAM memory (synchronous dynamic random access memory) when data is transferred from the non-volatile memory to the SDRAM memory;

wherein the non-volatile memory is slower than the SRAM memory;

wherein the non-volatile memory has a greater storage capacity than the SRAM memory;

wherein the non-volatile memory is slower than the SDRAM memory;

wherein the non-volatile memory has a greater storage capacity than the SDRAM memory; and

wherein the SDRAM memory is slower than the SRAM memory.

6. The method of claim 5, wherein the non-volatile memory comprises at least one flash memory device.

7. The method of claim 5, wherein the DMA controller comprises at least a first IO (input/output) interface controller;

wherein the method further comprises;

transferring, by the first IO interface DMA controller, data between the SDRAM memory and the hard disk drive.

8. The method of claim 7, wherein the DMA controller further comprises a second IO (input/output) interface controller;

wherein the method further comprises;

transferring, by the second IO interface DMA controller, data between the host and the SRAM memory.

14. The method of claim 5, wherein if the write data in the SRAM memory is clean prior to writing the new write data to the SRAM memory, then overwriting the write data in the SRAM memory.

9. An article of manufacture, comprising:

a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to;

buffer, in an SRAM memory (static random access memory), write data from a host;

transfer, by a flash interface controller, data between the SRAM memory and a non-volatile memory;

wherein said transfer comprises;

if the non-volatile memory is not full, then copying, by the flash interface controller, the write data from the SRAM memory to the non-volatile memory if a pre-defined threshold of unused cache lines is reached in the SRAM memory or if the write data in the SRAM memory is dirty prior to writing new write data to the SRAM memory;

if the non-volatile memory is full, then a DMA (Direct Memory Access) controller is configured to flush the write data from the SRAM memory to a hard disk drive if the pre-defined threshold of unused cache lines is reached in the SRAM memory or if the write data in the SRAM memory is dirty prior to writing new write data to the SRAM memory;

wherein the flash interface controller copies data from the non-volatile memory to an SDRAM memory (synchronous dynamic random access memory) when data is transferred from the non-volatile memory to the SDRAM memory;

wherein the non-volatile memory is slower than the SRAM memory;

wherein the non-volatile memory has a greater storage capacity than the SRAM memory;

wherein the non-volatile memory is slower than the SDRAM memory;

wherein the non-volatile memory has a greater storage capacity than the SDRAM memory; and

wherein the SDRAM memory is slower than the SRAM memory.

10. The article of manufacture of claim 9, wherein the non-volatile memory comprises at least one flash memory device.

11. The article of manufacture of claim 9, wherein the DMA controller comprises at least a first IO (input/output) interface controller;

wherein the non-transitory computer-readable medium further has stored thereon instructions that are configured to;

transfer, by the first IO interface DMA controller, data between the SDRAM memory and the hard disk drive.

12. The article of manufacture of claim 11, wherein the DMA controller comprises a second IO (input/output) interface controller;

wherein the non-transitory computer-readable medium further has stored thereon instructions that are configured to;

transfer, by the second IO interface DMA controller, data between the host and the SRAM memory.

15. The article of manufacture of claim 9, wherein the non-transitory computer-readable medium further has stored thereon instructions that are configured to:

overwrite the write data in the SRAM memory if the write data in the SRAM memory is clean prior to writing the new write data to the SRAM memory.