QSPI based methods of simultaneously controlling multiple SPI peripherals

• US 9,734,099 B1
• Filed: 04/27/2017
• Issued: 08/15/2017
• Est. Priority Date: 04/27/2017
• Status: Active Grant

• Current Assignee: Micro Lambda Wireless, Inc.
• Original Assignee: Micro Lambda Wireless, Inc.
• Inventors: Argoetti, Shlomo
• Primary Examiner(s): Shyu, Jing-Yi
• Application Number:
  US15/499,640
• Time in Patent Office: 110 Days
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247

Abstract

System and method of using a processor driven master Quad-SPI (QSPI) bus or interface to simultaneously and time-synchronously transmit different streams of data from a FIFO buffer to a plurality of different slave SPI interface peripherals. Here the QSPI interface data ports are configured to simultaneously transmit multiple 1 bit wide streams of different binary data and different chip select commands on an SPI clock cycle synchronized basis. Additional SPI slave peripherals may be controlled by use of additional non-SPI clock synchronized GPIO chip select commands and suitable logic gates. These methods are useful for creating a variety of embedded systems with faster response speeds, such as improved microwave frequency synthesizers with faster frequency changing times.

Claims

1. A method of using a processor driven master QSPI (Quad Serial Peripheral Interface) interface to simultaneously and time-synchronously transmit data from a FIFO (First In First Out) buffer to a plurality of slave SPI interface peripherals, said method comprising:

using said processor to load said FIFO buffer for said master QSPI interface with at least two streams of time-synchronized data intended for simultaneous transmission to said plurality of slave SPI interface peripherals, wherein said FIFO buffer comprises a FIFO memory width of at least 4 bits;

said master QSPI interface comprising at least a processor controlled SCLK (SPI Clock) clock output, and at least four FIFO buffer controlled QSPI data outputs configured to simultaneously transmit, in a processor controlled clock synchronized manner, at least four bits from said FIFO memory width, per SCLK clock cycle, from said FIFO buffer;

each of said plurality of slave SPI interface peripherals comprising at least a SCLK clock input, a SS (Slave Select) chip select input, and a MOSI (Master Output Slave Input) input configured to receive data from said master QSPI interface;

wherein said processor is configured to load said FIFO buffer with said at least two streams of time synchronized data,

each stream occupying its own data stream specific bit position of said FIFO memory width, so that all streams can simultaneously occupy their own portions of said FIFO memory width when said FIFO buffer is transmitted, thus creating at least two Time Synchronized Data (TSD) lines over at least two of said FIFO buffer controlled QSPI data outputs;

wherein said processor is further configured to load said FIFO buffer with at least one stream of slave SPI peripheral chip select commands configured to control when each of said plurality of slave SPI interface peripherals is to receive its particular stream of time synchronized data, each stream of slave SPI peripheral chip select commands occupying its own command stream specific bit position of said FIFO memory width when said FIFO buffer is transmitted, thus creating at least one Time Synchronized Programmable Chip Select (TSPCS) lines over at least one of said FIFO buffer controlled QSPI data outputs; and

using said processor, said FIFO buffer, and said master QSPI interface to use said processor controlled SCLK clock output, and at least three of said four FIFO buffer controlled QSPI data outputs to simultaneously transmit said at least two streams of time synchronized data and said at least one stream of slave SPI peripheral chip select commands to said plurality of SPI interface peripherals.

2. The method of claim 1, further using at least one logic gate to intercept said at least one stream of slave SPI peripheral chip select commands, and to use at least one logical operation on said at least one stream of slave SPI peripheral chip select commands to then control at least some SS chip select inputs on at least some of said slave SPI interface peripherals, thereby directing said streams of time synchronized data to selected slave SPI interface peripherals.

3. The method of claim 2, wherein said at least one logic gate is at least one “

OR”

gate, and said at least one logical operation is an “

OR”

operation.

4. The method of claim 2, wherein said processor further comprises at least one general purpose output comprising at least one GPIO (General Purpose Input Output) output, further using said processor and said at least one GPIO output to send additional chip select commands to said at least one logic gate.

5. The method of claim 4, wherein said at least one logic gate is at least one “

OR”

gate, and said at least one logical operation is an “

OR”

operation, further using said additional chip select commands from said at least one GPIO output to control said at least some SS chip select inputs on at least some of said SPI interface peripherals.

6. The method of claim 4, wherein said processor driven master QSPI interface further comprises at least one processor controlled chip select output;

and

further using said processor and said at least one processor controlled chip select output to send additional chip select commands to said at least one logic gate.

7. The method of claim 1, wherein at least two of said plurality of SPI interface peripherals are configured to accept SPI data of different lengths, at least one length being a shorter length, and another length being a longer length;

further using said processor to adjust said at least two streams of time synchronized data in said FIFO buffer to a same length by padding said shorter length of said time synchronized data stream with null bits; and

further using said processor to load said FIFO buffer with at least one stream of slave SPI peripheral chip select commands configured to control when both an SPI interface peripheral configured to read said shorter length is to read such data, and when an SPI interface peripheral configured to read said longer length is to read such data.

8. The method of claim 1, wherein said processor driven master QSPI interface also comprises a master Octal SPI interface.

9. The method of claim 1, wherein said FIFO buffer is a software or firmware implemented FIFO buffer residing in at least one of general purpose memory and processor general purpose memory, and wherein said processor uses said software or firmware to load said software or firmware implemented FIFO buffer.

10. The method of claim 1, wherein said plurality of slave SPI interface peripherals further comprise a MISO output to transmit data to said master QSPI interface;

further using said processor driven master QSPI interface and said FIFO buffer to receive at least two streams of time synchronized data transmitted by said MISO outputs of said plurality of slave SPI interface peripherals, each stream occupying its own data stream specific bit of said FIFO memory width.

11. The method of claim 1 wherein at least some of said plurality of slave SPI interface peripherals are used in a fast switching microwave frequency synthesizer.

12. The method of claim 1, wherein said master QSPI interface comprises four FIFO buffer controlled QSPI data outputs, and wherein said FIFO buffer comprises a FIFO memory width of 4 bits;

using two of said FIFO buffer controlled QSPI data outputs to transmit two said Time Synchronized Data (TSD) lines; and

using two of said FIFO buffer controlled QSPI data outputs to transmit two Time Synchronized Programmable Chip Select (TSPCS) lines.

13. A method of using a processor driven master QSPI (Quad Serial Peripheral Interface) interface to simultaneously and time-synchronously transmit data from a FIFO (First In First Out) buffer to a plurality of slave SPI interface peripherals, said method comprising:

using said processor to load said FIFO buffer for said master QSPI interface with at least two streams of time-synchronized data intended for simultaneous transmission to said plurality of slave SPI interface peripherals, wherein said FIFO buffer comprises a FIFO memory width of at least 4 bits;

said master QSPI interface comprising at least a processor controlled SCLK (SPI Clock) clock output, and at least four FIFO buffer controlled QSPI data outputs configured to simultaneously transmit, in a processor controlled clock synchronized manner, at least four bits from said FIFO memory width, per SCLK clock cycle, from said FIFO buffer;

each of said plurality of slave SPI interface peripherals comprising at least a SCLK clock input, a SS (Slave Select) chip select input, and a MOSI (Master Output Slave Input) input configured to receive data from said master QSPI interface;

wherein said processor is configured to load said FIFO buffer with said at least two streams of time synchronized data, each stream occupying its own data stream specific bit position of said FIFO memory width, so that all streams can simultaneously occupy their own portions of said FIFO memory width when said FIFO buffer is transmitted, thus creating at least two Time Synchronized Data (TSD) lines over at least two of said FIFO buffer controlled QSPI data outputs;

wherein said processor is further configured to load said FIFO buffer with at least one stream of slave SPI peripheral chip select commands configured to control when each of said plurality of slave SPI interface peripherals is to receive its particular stream of time synchronized data, each stream of slave SPI peripheral chip select commands occupying its own command stream specific bit position of said FIFO memory width when said FIFO buffer is transmitted, thus creating at least one Time Synchronized Programmable Chip Select (TSPCS) lines over at least one of said FIFO buffer controlled QSPI data outputs; and

using said processor, said FIFO buffer, and said master QSPI interface to use said processor controlled SCLK clock output, and at least three of said four FIFO buffer controlled QSPI data outputs to simultaneously transmit said at least two streams of time synchronized data and said at least one stream of slave SPI peripheral chip select commands to said plurality of SPI interface peripherals;

wherein at least some of said plurality of slave SPI interface peripherals are used in a fast switching microwave frequency synthesizer;

further using at least one logic gate to intercept said at least one stream of slave SPI peripheral chip select commands, and to use at least one logical operation on said at least one stream of slave SPI peripheral chip select commands to then control at least some SS chip select inputs on at least some of said slave SPI interface peripherals, thereby directing said streams of time synchronized data to selected slave SPI interface peripherals;

wherein said processor further comprises at least one general purpose output comprising at least one GPIO (General Purpose Input Output) output, further using said processor and said at least one GPIO output to send additional chip select commands to said at least one logic gate.

14. The method of claim 13, wherein said at least one logic gate is at least one “

OR”

gate, and said at least one logical operation is an “

OR”

operation.

15. The method of claim 13, wherein at least two of said plurality of SPI interface peripherals are configured to accept SPI data of different lengths, at least one length being a shorter length, and another length being a longer length;

further using said processor to adjust said at least two streams of time synchronized data in said FIFO buffer to a same length by padding said shorter length of said time synchronized data stream with null bits; and

further using said processor to load said FIFO buffer with at least one stream of slave SPI peripheral chip select commands configured to control when both an SPI interface peripheral configured to read said shorter length is to read such data, and when an SPI interface peripheral configured to read said longer length is to read such data.

16. The method of claim 13, wherein said processor driven master QSPI interface also comprises a master Octal SPI interface.

17. The method of claim 13, wherein said FIFO buffer is a software or firmware implemented FIFO buffer residing in at least one of general purpose memory and processor general purpose memory, and wherein said processor uses said software or firmware to load said software or firmware implemented FIFO buffer.