Data storage device and method for integrated bridge firmware to be retrieved from a storage system on chip (SOC)

• US 9,734,117 B2
• Filed: 01/26/2015
• Issued: 08/15/2017
• Est. Priority Date: 01/26/2015
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: McCabe, Timothy J., Maroney, John E.
• Primary Examiner(s): Yi, David X
• Assistant Examiner(s): GRULLON, FRANCISCO A
• Application Number:
  US14/605,910
• Publication Number:
  US 20160217099A1
• Time in Patent Office: 932 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/4063 Device-to-bus coupling
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data storage device may comprise a first non-volatile memory, configured to store storage System-On-Chip (SOC) data and protocol bridge data; a storage SOC comprising circuitry configured to control the data storage device and to, upon power-on, retrieve the storage SOC data from the first non-volatile memory and configure itself according to the retrieved storage SOC data; a bus coupled to the storage SOC; and a protocol bridge coupled to the bus and comprising circuitry configured to translate between a first and a second communication protocol and to, upon power-on, retrieve the protocol bridge data from the first non-volatile memory via the storage SOC and the bus and configure itself according to the retrieved protocol bridge data.

Claims

1. A data storage device, comprising:

a first non-volatile memory, configured to store a second portion of storage System-On-Chip (SOC) instructions and data and a second portion of protocol bridge instructions and data;

a storage SOC configured to control the data storage device and comprising second non-volatile memory configured to store a first portion of SOC instructions and data, the storage SOC comprising circuitry configured to execute the first portion of SOC instructions and data upon power-on and to enable the storage SOC to retrieve the second portion of storage SOC instructions and data from the first non-volatile memory and configure itself according to at least the retrieved second portion of storage SOC instructions and data;

a bus coupled to the storage SOC; and

a protocol bridge coupled to the bus and comprising;

circuitry configured to translate between a first and a second communication protocol; and

third non-volatile memory configured to store a first portion of protocol bridge instructions and data that, when retrieved and executed, enables the protocol bridge to activate the bus upon power-on, and enables the protocol bridge to retrieve the second portion of protocol bridge instructions and data from the first non-volatile memory via the storage SOC and the activated bus and configure itself according to at least the retrieved second portion of protocol bridge instructions and data.

2. The data storage device of claim 1, further comprising first volatile memory and wherein the storage SOC is further configured to load at least the second portion of storage SOC instructions and data retrieved from the first non-volatile memory into the first volatile memory.

3. The data storage device of claim 2, wherein the circuitry in the protocol bridge further comprises second volatile memory and wherein the first non-volatile memory is further configured to store overlay protocol bridge instructions and data and wherein the circuitry in the protocol bridge is further configured to, after having configured itself, retrieve the overlay protocol bridge instructions and data from the first non-volatile memory via the storage SOC and the activated bus and to store the retrieved overlay protocol bridge instructions and data in the second volatile memory.

4. The data storage device of claim 1, wherein the circuitry in the protocol bridge further comprises second volatile memory and wherein the protocol bridge is further configured to load at least the second portion of protocol bridge instructions and data retrieved, via the storage SOC and the activated bus, from the first non-volatile memory into the second volatile memory.

5. The data storage device of claim 1, wherein a portion of the first non-volatile memory is configured as user-accessible memory.

6. The data storage device of claim 1, further comprising primary non-volatile storage memory that is separate from the first non-volatile memory, at least a portion of the primary non-volatile storage memory being user-accessible.

7. The data storage device of claim 1, wherein the circuitry in the protocol bridge is configured to repeatedly retrieve parts of the second portion of protocol bridge instructions and data from the first non-volatile memory in blocks of a predetermined size.

8. A method of configuring and operating a data storage device comprising first non-volatile memory, a storage System-On-Chip (SOC) coupled to the first non-volatile, memory and comprising a second non-volatile memory, a bus coupled to the storage SOC and a protocol bridge coupled to the bus, the protocol bridge comprising a third non-volatile memory and being configured to translate between a first and a second communication protocol, the method comprising:

storing a first portion of storage SOC instructions and data in the second non-volatile memory and storing a first portion of protocol bridge instructions and data in the third non-volatile memory;

storing a second portion of storage SOC instructions and data and a second portion of protocol bridge instructions and data in the first non-volatile memory; and

upon power-on of the data storage device;

retrieving the first portion of storage SOC instructions and data from the second non-volatile memory, the retrieved first portion of storage SOC instructions and data enabling the storage SOC to retrieve the second portion of SOC instructions and data from the first non-volatile memory and to configure the storage SOC according to the retrieved first and second portions of storage SOC instructions and data; and

retrieving the first portion of protocol bridge instructions data from the third non-volatile memory, activating the bus using the first portion of protocol bridge instructions and data retrieved from the third non-volatile memory and retrieving the second portion of protocol bridge instructions and data from the first non-volatile memory via the storage SOC and the activated bus and configuring the protocol bridge according to the retrieved first and second portions of the protocol bridge instructions and data.

9. The method of claim 8, wherein the storage SOC further comprises first volatile memory and wherein the method further comprises loading at least the second portion of storage SOC instructions and data retrieved from the first non-volatile memory into the first volatile memory.

10. The method of claim 9, wherein the protocol bridge further comprises second volatile memory and the method further comprises, after the protocol bridge has configured itself, retrieving overlay protocol bridge instructions and data from the first non-volatile memory via the storage SOC and the activated bus and storing the retrieved overlay protocol bridge instructions and data in the second volatile memory.

11. The method of claim 8, wherein the protocol bridge further comprises second volatile memory and wherein the method further comprises loading at least the second portion of protocol bridge instructions and data retrieved, via the storage SOC and the activated bus, from the first non-volatile memory into the second volatile memory.

12. The method of claim 8, wherein a portion of the first non-volatile memory is configured as user-accessible memory.

13. The method of claim 8, performed with the data storage device further comprising primary non-volatile storage memory that is separate from the first non-volatile memory, at least a portion of the primary non-volatile storage memory being user-accessible.

14. The method of claim 8, further comprising the protocol bridge repeatedly retrieving parts of the second portion of protocol bridge instructions and data from the first non-volatile memory in blocks of a predetermined size.

15. Circuitry for a data storage device, comprising:

a first non-volatile memory, configured to store a second portion of storage System-On-Chip (SOC) instructions and data and a second portion of protocol bridge instructions and data;

a storage SOC configured to control the data storage device and comprising second non-volatile memory configured to store a first portion of SOC instructions and data, the storage SOC comprising circuitry configured to execute the first portion of SOC instructions and data upon power-on and to enable the storage SOC to retrieve the second portion of storage SOC instructions and data from the first non-volatile memory and configure itself according to at least the retrieved second portion of storage SOC instructions and data;

a bus coupled to the storage SOC; and

a protocol bridge coupled to the bus and comprising;

circuitry configured to translate between a first and a second communication protocol; and

third non-volatile memory configured to store a first portion of protocol bridge instructions and data that, when retrieved and executed, enables the protocol bridge to activate the bus upon power-on, and enables the protocol bridge to retrieve the second portion of protocol bridge instructions and data from the first non-volatile memory via the storage SOC and the activated bus and configure itself according to at least the retrieved second portion of protocol bridge instructions and data.