Shielded vertically stacked data line architecture for memory
First Claim
Patent Images
1. A method comprising:
- applying a pass voltage to unselected access lines of a plurality of access lines;
applying an operational voltage to selected access lines of the plurality of access lines to enable particular memory cells;
enabling first shield transistors that couple first alternating data lines of a plurality of vertically stacked data lines to a shield voltage line; and
disabling second shield transistors that couple second alternating data lines of the plurality of vertically stacked data lines to the shield voltage line,wherein strings of memory cells comprising the enabled memory cells are operably coupled to the second alternating data lines and strings of memory cells that do not comprise the enabled memory cells are operably coupled to the first alternating data lines.
7 Assignments
0 Petitions
Accused Products
Abstract
Apparatuses and methods include an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines, and the use thereof. A data line of the first plurality of data lines is coupled to the first string through a first select device. A data line of the second plurality of data lines is coupled to the second string through a second select device and is adjacent to the data line coupled to the first string. Such an apparatus can be configured to couple the data line coupled to the first string to a shield potential during at least a portion of a memory operation involving a memory cell of the second string.
-
Citations
20 Claims
-
1. A method comprising:
-
applying a pass voltage to unselected access lines of a plurality of access lines; applying an operational voltage to selected access lines of the plurality of access lines to enable particular memory cells; enabling first shield transistors that couple first alternating data lines of a plurality of vertically stacked data lines to a shield voltage line; and disabling second shield transistors that couple second alternating data lines of the plurality of vertically stacked data lines to the shield voltage line, wherein strings of memory cells comprising the enabled memory cells are operably coupled to the second alternating data lines and strings of memory cells that do not comprise the enabled memory cells are operably coupled to the first alternating data lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A method comprising:
-
applying a read voltage to selected access lines of a plurality of access lines to enable particular memory cells; applying a read pass voltage to unselected access lines of the plurality of access lines; applying a pre-charge voltage to first alternating data lines of a plurality of vertically stacked data lines; applying a shield voltage to second alternating data lines of the plurality of vertically stacked data lines; applying an enable voltage to select gate drain transistors that couple first memory cell strings, comprising the enabled memory cells, to the first alternating data lines; and applying a disable voltage to select gate drain transistors that couple second memory cell strings that do not comprise the enabled memory cells. - View Dependent Claims (11, 12, 13, 14)
-
-
15. A method comprising:
-
applying a programming voltage to a selected access line of a plurality of access lines to program a selected memory cell in a first string of memory cells; applying a program pass voltage to unselected access lines of the plurality of access lines to disable unselected memory cells; applying page buffer data to a first data line, of a plurality of vertically stacked alternating data lines, operably coupled to the first string of memory cells; applying a shield voltage to adjacent data lines, of the plurality of vertically stacked alternating data lines, that are adjacent to the first data line and on either side of the first data line, the adjacent data lines coupled to unselected strings of memory cells; applying an enable voltage to select gate drain transistors to operably couple the first string of memory cells to the first data line; and applying a disable voltage to select gate drain transistors that couple the unselected strings of memory cells to the adjacent data lines. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification