Memory repair using external tags

• US 9,734,921 B2
• Filed: 10/31/2013
• Issued: 08/15/2017
• Est. Priority Date: 11/06/2012
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Rajan, Suresh, Shaeffer, Ian
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US14/407,318
• Publication Number:
  US 20150162101A1
• Time in Patent Office: 1,384 Days
• Field of Search: 714710, 714711, 714764, 714768
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

A memory device (100) includes an extra column (114) of repair memory tiles. These repair memory tiles are accessed at the same time, and in the same manner as the main array of memory tiles. The output of the repair column is substituted for the output of a column of the main array (112). The main array column that is substituted is determined by tags (121) stored externally to the memory device. The external tags are queried with a partial address of the access. If the address of the access corresponds to an address in the external tags, the tag information is supplied to the memory device. The tag information determines which column in the main array is replaced by the output of the repair column. Since each column of the main array supplies one bit during the access, the repair column enables cell-by-cell replacement of main array cells.

Claims

1. A memory integrated circuit, comprising:

a memory array having a plurality of columns and a plurality of rows, the memory array comprising at least one repair column comprising at least one repair element, each of the at least one repair elements comprising at least one repair cell;

an external command/address interface to receive a command, a row address, and a column address from a source external to the memory integrated circuit, the row address to select a row of the plurality of rows to output a row of data, the column address to select a subset of the row of data; and

,

an external repair address interface to receive a repair enable indicator and a repair address from the source external to the memory integrated circuit, the repair address corresponding to a column of a subset of the plurality of rows, the memory integrated circuit to determine, based on the command and the repair enable indicator, whether data from the repair column is to be output by the memory.

2. The memory of claim 1, wherein the data from the at least one repair column replaces data from one of the plurality of columns.

3. The memory of claim 1, wherein the data from the at least one repair column is to be used as syndrome bits for an error detect and correct code used to correct data from one of the plurality of columns.

4. The memory of claim 1 wherein the command, row address, and column address are to be received synchronously with respect to an external timing reference signal, and the repair address is to be received synchronously with respect to the external timing reference signal.

5. The memory of claim 1, wherein a second repair address can be received before the data from the repair column is to be output by the memory.

6. The memory of claim 1, further comprising:

self-test circuitry to detect a cell that meets a criteria for designation as a failing cell.

7. The memory of claim 6, wherein the failing cell address is to be coupled to a nonvolatile memory.

8. A memory module, comprising:

a plurality of memory integrated circuits comprising at least a first memory integrated circuit and a second memory integrated circuit, the first memory integrated circuit having a first repair memory subarray, the second memory integrated circuit having a second repair memory subarray;

a first address bus, external to the plurality of memory integrated circuits, to distribute row and column access addresses to the plurality of memory integrated circuits; and

,

a second address bus, external to the plurality of memory integrated circuits, to distribute repair addresses to the plurality of memory integrated circuits, the second address bus to also cause the first memory integrated circuit to output data stored in the first repair memory subarray and to cause the second memory integrated circuit not to output data stored in the second memory subarray.

9. The memory module of claim 8, further comprising:

a buffer integrated circuit, the buffer integrated circuit to drive the first address bus and the second address bus.

10. The memory module of claim 9, further comprising:

a nonvolatile memory device, the nonvolatile memory device coupled to the buffer integrated circuit to provide the buffer integrated circuit with a repair address, the buffer integrated circuit to drive the second address bus with a first part of the repair address.

11. The memory module of claim 9, wherein the buffer integrated circuit further comprises a nonvolatile memory to store a repair address, the buffer integrated circuit to drive the second address bus with a first part of the repair address.

12. The memory module of claim 10, wherein the buffer integrated circuit is to drive a control indicator, the control indicator to cause the first memory integrated circuit to output data stored in the first repair memory subarray.

13. The memory module of claim 10, wherein an access address is to be received, by the plurality of memory integrated circuits and on the first address bus, synchronously with respect to a timing reference signal, and a repair address is to be received, by the plurality of memory integrated circuits and on the second address bus, synchronously with respect to the timing reference signal.

14. The memory module of claim 10, further comprising:

a buffer integrated circuit, the buffer integrated circuit to drive the first address bus and the second address bus, the buffer integrated circuit to receive from the first memory integrated circuit a failing cell address that is associated with a cell that meets a criteria for designation as a failing cell.

15. A method of repairing a first memory integrated circuit of a plurality of memory integrated circuits that reside on a common substrate, comprising:

storing a repair address in an integrated circuit, the repair address corresponding to a column of a subset of rows of the first memory integrated circuit;

receiving, by the integrated circuit, an access address that matches the repair address; and

,

in response to receiving the access address that matches the repair address, outputting, by the integrated circuit, an external repair indicator to the plurality of memory integrated circuits, the external repair indicator to indicate the first memory integrated circuit is to output data stored in a respective internal repair sub-array, the external repair indicator to also indicate that at least one of the plurality of memory integrated circuits are not to output data stored in a corresponding respective internal repair sub-array.

16. The method of claim 15, wherein the data from the respective internal repair sub-array replaces data from a sub-array of a plurality of sub-arrays storing data in the first memory integrated circuit.

17. The method of claim 15, further comprising:

receiving a failing cell address associated with a failing cell from the first memory integrated circuit.

18. The method of claim 17, wherein the failing cell address is received on an interface that outputs the external repair indicator to the plurality of memory integrated circuits.

19. The method of claim 18, further comprising:

storing the failing cell address in a nonvolatile memory.

20. The method of claim 19, wherein the nonvolatile memory is disposed on the integrated circuit.