Semiconductor device interconnect structures formed by metal reflow process

• US 9,735,051 B2
• Filed: 12/14/2015
• Issued: 08/15/2017
• Est. Priority Date: 12/14/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Murray, Conal E., Yang, Chih-Chao
• Primary Examiner(s): Nguyen, Thanh T
• Application Number:
  US14/967,618
• Publication Number:
  US 20170170062A1
• Time in Patent Office: 610 Days
• Field of Search: None
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76882 Reflowing or applying of pressure to better fill the contact hole
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53209 based on metals, e.g. alloys, metal silicides H01L23/53285 takes precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers

Abstract

Methods are devices are provided in which interconnection structures are formed using metal reflow techniques. For example, a method to fabricate a semiconductor device includes forming an opening in an ILD (inter-level dielectric) layer. The opening includes a via hole and a trench. A layer of diffusion barrier material is deposited to cover the ILD layer and to line the opening with the diffusion barrier material. A layer of first metallic material is deposited on the layer of diffusion barrier material to cover the ILD layer and to line the opening with the first metallic material. A reflow process is performed to allow the layer of first metallic material to reflow into the opening and at least partially fill the via hole with the first metallic material. A layer of second metallic material is deposited to at least partially fill a remaining portion of the opening in the ILD layer.

Claims

1. A method to fabricate a semiconductor device, comprising:

forming a dual damascene opening in an ILD (inter-level dielectric) layer, wherein the dual damascene opening comprises a via opening and a trench opening which is disposed over the via opening;

depositing a layer of diffusion barrier material to cover the ILD layer and to line the via opening and the trench opening with the diffusion barrier material;

depositing a layer of first metallic material on the layer of diffusion barrier material to cover the ILD layer with overburden first metallic material and to line the via opening and the trench opening with a layer of the first metallic material;

performing a reflow process by thermal annealing at a temperature which causes the layer of first metallic material to melt and allow at least a melted portion of the overburden first metallic material on the ILD layer and at least a melted portion of the layer of first metallic material which lines the trench opening to reflow into the via opening and at least partially fill the via opening with the melted first metallic material; and

depositing a layer of second metallic material on the reflowed first metallic material to at least partially fill a remaining portion of the dual damascene opening in the ILD layer,

wherein the first metallic material comprises cobalt.

2. The method of claim 1, wherein the layer of first metallic material is deposited using a PVD (physical vapor deposition) process.

3. The method of claim 1, wherein depositing a layer of second metallic material to at least partially fill a remaining portion of the opening in the ILD layer comprises depositing copper using an electroplating process to completely fill the remaining portion of the opening with copper.

4. The method of claim 1, wherein the reflow process is performed to at least completely fill the via hole with the first metallic material.

5. The method of claim 1, wherein the reflow process is performed by thermal annealing in a temperature range of about 200 degrees Celsius to about 500 degrees Celsius.

6. The method of claim 1, further comprising performing a reflow process to allow the layer of second metallic material to melt and reflow and at least one of partially fill the remaining portion of the dual damascene opening and completely fill the remaining portion of the dual damascene opening, wherein the first and second metallic materials are the same.

7. The method of claim 1, wherein the ILD layer is formed as part of a BEOL (back-end-of-line) structure.

8. The method of claim 1, wherein the second metallic material comprises copper.

9. The method of claim 1, wherein performing the reflow process comprises leaving a thin layer of the reflowed first metallic material on sidewall surfaces of the remaining portion of the dual damascene opening in the ILD layer at a termination of the reflow process, wherein the thin layer of the reflowed first metallic material serves as a liner layer on which the layer of second metallic material is deposited to fill the remaining portion of the dual damascene opening in the ILD layer.

10. A semiconductor device formed by a process comprising:

forming a dual damascene opening in an ILD (inter-level dielectric) layer, wherein the dual damascene opening comprises a via opening and a trench opening which is disposed over the via opening;

depositing a layer of diffusion barrier material to cover the ILD layer and to line the via opening and the trench opening with the diffusion barrier material;

depositing a layer of first metallic material on the layer of diffusion barrier material to cover the ILD layer with overburden first metallic material and to line the via opening and the trench opening with a layer of the first metallic material;

performing a reflow process by thermal annealing at a temperature which causes the layer of first metallic material to melt and allow at least a melted portion of the overburden first metallic material on the ILD layer and at least a melted portion of the layer of first metallic material which lines the trench opening to reflow into the via opening and at least partially fill the via opening with the melted first metallic material; and

depositing a layer of second metallic material on the reflowed first metallic material to at least partially fill a remaining portion of the dual damascene opening in the ILD layer,

wherein the first metallic material comprises cobalt.

11. The semiconductor device of claim 10, wherein the layer of first metallic material is deposited using a PVD (physical vapor deposition) process.

12. The semiconductor device of claim 10, wherein depositing a layer of second metallic material to at least partially fill a remaining portion of the opening in the ILD layer comprises depositing copper using an electroplating process to completely fill the remaining portion of the opening with copper.

13. The semiconductor device of claim 10, wherein the reflow process is performed to at least completely fill the via hole with the first metallic material.

14. The semiconductor device of claim 10, wherein the process further comprises performing a reflow process to allow the layer of second metallic material to melt and reflow and at least one of partially fill the remaining portion of the dual damascene opening and completely fill the remaining portion of the dual damascene opening, wherein the first and second metallic materials are the same.

15. The semiconductor device of claim 10, wherein the semiconductor device comprises a BEOL (back-end-of-line) structure.

16. The semiconductor device of claim 10, wherein the second metallic material comprises copper.

17. The semiconductor device of claim 10, wherein performing the reflow process comprises leaving a thin layer of the reflowed first metallic material on sidewall surfaces of the remaining portion of the dual damascene opening in the ILD layer at a termination of the reflow process, wherein the thin layer of the reflowed first metallic material serves as a liner layer on which the layer of second metallic material is deposited to fill the remaining portion of the dual damascene opening in the ILD layer.