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Method for producing a plurality of measurement regions on a chip, and chip with measurement regions

  • US 9,735,072 B2
  • Filed: 05/30/2014
  • Issued: 08/15/2017
  • Est. Priority Date: 05/30/2013
  • Status: Active Grant
First Claim
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1. Chip having a plurality of electrically addressable measurement regions, wherein a compartmental structure separates the measurement regions from one another on the chip surface, wherein the compartmental structure has a hydrophobic layer, wherein the hydrophobic layer contains a photoresist or is a photoresist and wherein the chip surface is planar and the compartmental structure is raised relative thereto.

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