Bond via array for thermal conductivity

• US 9,735,084 B2
• Filed: 12/11/2014
• Issued: 08/15/2017
• Est. Priority Date: 12/11/2014
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Katkar, Rajesh, Gao, Guilian, Woychik, Charles G., Zohni, Wael
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): TYNES JR., LAWRENCE C
• Application Number:
  US14/567,918
• Publication Number:
  US 20160172268A1
• Time in Patent Office: 978 Days
• Field of Search: 257691
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

In a microelectronic device, a substrate has first upper and lower surfaces. An integrated circuit die has second upper and lower surfaces. Interconnects couple the first upper surface of the substrate to the second lower surface of the integrated circuit die for electrical communication therebetween. A via array has proximal ends of wires thereof coupled to the second upper surface for conduction of heat away from the integrated circuit die. A molding material is disposed in the via array with distal ends of the wires of the via array extending at least to a superior surface of the molding material.

Claims

1. A microelectronic device, comprising:

a substrate having a first upper surface and a first lower surface;

an integrated circuit die having a second upper surface and a second lower surface;

interconnects coupling the first upper surface of the substrate to the second lower surface of the integrated circuit die for electrical communication therebetween;

a bond via array having proximal ends of wire bond wires thereof ball bonded to the second upper surface for conduction of heat away from the integrated circuit die to and through the wire bond wires of the bond via array to the second upper surface; and

a molding material disposed in the bond via array with distal ends of the wire bond wires of the bond via array extending at least to a superior surface of the molding material.

2. The microelectronic device according to claim 1, further comprising:

a metalization layer disposed over the second upper surface of the integrated circuit die for coupling the proximal ends of the wire bond wires of the bond via array to the second upper surface for the conduction;

a heat sink disposed above the distal ends of the wire bond wires; and

a thermally conductive material disposed in contact with the distal ends of the wire bond wires and a lower surface of the heat sink for coupling the distal ends of the wire bond wires and the heat sink for thermal conductivity.

3. The microelectronic device according to claim 2, wherein the wire bond wires are first wire bond wires, the microelectronic device further comprising second wire bond wires coupling the second upper surface to the first upper surface of the substrate for the conduction.

4. The microelectronic device according to claim 1, wherein:

the proximal ends of the wire bond wires of the bond via array are first proximal ends of first wire bond wires of a first bond via array, respectively; and

the microelectronic device further comprising a second bond via array having second proximal ends of second wire bond wires thereof coupled to the second upper surface for the conduction of heat away from the integrated circuit die.

5. The microelectronic device to claim 4, wherein the first bond via array is denser than the second bond via array.

6. The microelectronic device to claim 5, wherein the first bond via array is disposed over a hot spot of the integrated circuit die.

7. The microelectronic device to claim 6, wherein:

the distal ends of the first wire bond wires of the first bond via array are first distal ends of first wire bond wires of a first bond via array, respectively; and

second distal ends of the second wire bond wires of the second bond via array are more widely dispersed than the first distal ends of the first wire bond wires of the first bond via array.

8. The microelectronic device to claim 7, wherein the first distal ends of the first wire bond wires of the first bond via array and the second distal ends of the second wire bond wires of the second bond via array do not come into contact with the lower surface of the heat sink.

9. The microelectronic device to claim 1, wherein the substrate is a package substrate.

10. A microelectronic device, comprising:

a package substrate having a first upper surface and a first lower surface;

an interposer substrate having a second upper surface and a second lower surface;

first interconnects coupling the second lower surface and the first upper surface to one another;

an integrated circuit die having a third upper surface and a third lower surface;

second interconnects coupling the second upper surface and the third lower surface to one another;

a die stack coupled to the interposer substrate;

wherein the die stack has a fourth upper surface higher than the third upper surface;

a bond via array having proximal ends of wire bond wires thereof ball bonded to the third upper surface for conduction of heat away from the integrated circuit die to and through the wire bond wires of the bond via array to the third upper surface; and

a molding material disposed in the bond via array with distal ends of the wire bond wires of the bond via array extending at least to a superior surface of the molding material and higher than the fourth upper surface of the die stack.

11. The microelectronic device according to claim 10, further comprising:

a metallization layer disposed over the second upper surface of the integrated circuit die for wire bonds coupling the proximal ends of the wire bond wires of the bond via array to the third upper surface for the conduction;

a heat sink disposed above the distal ends of the wire bond wires; and

a thermally conductive material disposed in contact with the distal ends of the wire bond wires and a lower surface of the heat sink for coupling the distal ends of the wire bond wires and the heat sink for thermal conductivity.

12. The microelectronic device according to claim 11, further comprising a passivation layer disposed on the second upper surface of the integrated circuit die, wherein the metalization layer is disposed on the passivation layer.

13. The microelectronic device according to claim 10, wherein:

the proximal ends of the wire bond wires of the bond via array are first proximal ends of first wire bond wires of a first bond via array, respectively; and

the microelectronic device further comprising a second bond via array having second proximal ends of second wire bond wires thereof coupled to the third upper surface for the conduction of heat away from the integrated circuit die.

14. The microelectronic device according to claim 13, wherein the first bond via array is denser than the second bond via array.

15. The microelectronic device according to claim 14, wherein the first bond via array is disposed over a hot spot of the integrated circuit die.

16. The microelectronic device to claim 13, wherein:

the distal ends of the first wire bond wires of the first bond via array are first distal ends of first wire bond wires of a first bond via array, respectively; and

second distal ends of the second wire bond wires of the second bond via array are more widely dispersed than the first distal ends of the first wire bond wires of the first bond via array.

17. The microelectronic device to claim 16, wherein the first distal ends of the first wire bond wires of the first bond via array and the second distal ends of the second wire bond wires of the second bond via array do not come into contact with the lower surface of the heat sink.

18. A method for formation of a microelectronic device, comprising:

obtaining a substrate having a first upper surface and a first lower surface;

obtaining an integrated circuit die having a second upper surface and a second lower surface;

interconnecting with interconnects the first upper surface of the substrate to the second lower surface of the integrated circuit die for electrical conductivity therebetween;

forming a bond via array having proximal ends of wire bond wires thereof ball bonded to the second upper surface for conduction of heat away from the integrated circuit die to and through the wire bond wires of the bond via array to the second upper surface; and

depositing molding material in the bond via array with distal ends of the wire bond wires of the bond via array extending at least to a superior surface of the molding material.

19. The method according to claim 18, further comprising:

forming a passivation layer on the second upper surface of the integrated circuit die;

plating a metalization layer on the passivation layer for wire bonds for coupling the proximal ends of the wire bond wires of the bond via array to the second upper surface for the conduction;

applying a thermally conductive material for contact with the distal ends of the wire bond wires for thermally coupling the distal ends of the wire bond wires with a heat sink; and

placing a lower surface of the heat sink onto the thermally conductive material;

wherein the lower surface of the heat sink is located above the distal ends of the wire bond wires for contact with a lower surface of the heat sink.

20. The method according to claim 19, wherein the proximal ends of the wire bond wires of the bond via array are first proximal ends of first wire bond wires of a first bond via array, respectively;

and

the method further comprising forming a second bond via array having second proximal ends of second wire bond wires thereof coupled to the second upper surface for the conduction of heat away from the integrated circuit die.