Dual metal-insulator-semiconductor contact structure and formulation method

• US 9,735,111 B2
• Filed: 09/23/2015
• Issued: 08/15/2017
• Est. Priority Date: 09/23/2015
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.), International Business Machines Corporation
• Original Assignee: GlobalFoundries, Inc., International Business Machines Corporation
• Inventors: Niimi, Hiroaki, Ando, Takashi, Yamashita, Tenko
• Primary Examiner(s): Luu, Chuong A
• Application Number:
  US14/862,894
• Publication Number:
  US 20170084537A1
• Time in Patent Office: 692 Days
• Field of Search: 438197
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/285 from a gas or vapour, e.g. condensation
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

Claims

1. A method of making a semiconductor device, the method comprising:

forming a first source/drain trench over a first source/drain region in a first transistor and a second source/drain trench over a second source/drain region in a second transistor;

forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench;

forming a first source/drain contact over the first source/drain region, the first source/drain contact comprising a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and

forming a second source/drain contact over the second source/drain region, the second source/drain contact comprising a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material;

wherein the first tri-layer contact comprises a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact comprises a second metal oxide layer in contact with the second silicon dioxide layer.

2. The method of claim 1, wherein the first metal oxide layer is different than the second metal oxide layer.

3. The method of claim 1, wherein the first metal oxide layer is aluminum oxide, and the second metal oxide layer is lanthanum oxide.

4. The method of claim 1, further comprising disposing a conductive liner layer between the first silicon dioxide layer and the first tri-layer contact or the second silicon dioxide layer and the second tri-layer contact.

5. The method of claim 1, wherein the conductive liner layer comprises titanium nitride.

6. The method of claim 1, wherein the first tri-layer contact further comprises a layer of titanium disposed over the first metal oxide layer.

7. The method of claim 6, wherein the first tri-layer contact further comprises a layer of titanium nitride disposed between the layer of titanium and the first conductive material.

8. The method of claim 1, wherein the second tri-layer contact further comprises a layer of titanium disposed over the second metal oxide layer.

9. The method of claim 1, wherein the second tri-layer contact further comprises a layer of titanium disposed over the second metal oxide layer and a layer of titanium nitride disposed between the layer of titanium and the second conductive material.

10. A method of making a semiconductor device, the method comprising:

forming a first source/drain trench over a first source/drain region in a first transistor and a second source/drain trench over a second source/drain region in a second transistor;

forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench;

disposing a first metal oxide layer onto the first silicon dioxide layer and along a first sidewall of the first source/drain trench and over the second silicon dioxide layer and along a sidewall of the second source/drain trench;

removing the first metal oxide layer from the second source/drain trench;

disposing a second metal oxide layer followed by a conductive liner layer over the first metal oxide layer within the first source/drain trench and directly onto the second silicon dioxide layer and along the sidewall of the second source/drain trench;

removing by a selective process, the second metal oxide layer and the conductive liner layer from the first source/drain trench; and

filling the first source/drain trench and the second source/drain trench with a conductive material.

11. The method of claim 10, further comprising disposing a conductive layer over the first silicon dioxide layer within the first source/drain trench and removing the conductive layer from the first source/drain trench before disposing the first metal oxide layer.

12. The method of claim 10, further comprising disposing a conductive layer over the second silicon dioxide layer within the second source/drain trench before disposing the first metal oxide layer, and then removing the conductive layer along with the first metal oxide layer.

13. The method of claim 10, further comprising disposing a titanium layer and a titanium nitride layer between the conductive material and the first metal oxide layer within the first source/drain trench and between the conductive material and the second metal oxide layer within the second source/drain trench.

14. The method of claim 10, further comprising removing the conductive liner layer before filling the first source/drain trench and the second source/drain trench with the conductive material.

15. The method of claim 10, wherein the first metal oxide layer comprises aluminum oxide, and the second metal oxide layer comprises lanthanum oxide.

16. A method of making a semiconductor device, the method comprising:

forming a first source/drain trench over a first source/drain in a first transistor and a second source/drain trench over a second source/drain in a second transistor;

forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench, the first silicon dioxide layer directly contacting a top portion of the first source/drain, and the second silicon dioxide layer directly contacting a top portion of the second source/drain;

forming a first source/drain contact over the first source/drain, the first source/drain contact comprising a first tri-layer liner disposed between the first silicon dioxide layer and a first conductive material, the first tri-layer liner comprising a first metal oxide layer in contact with the first silicon dioxide layer; and

forming a second source/drain contact over the second source/drain, the second source/drain contact comprising a second tri-layer liner disposed between the second silicon dioxide layer and a second conductive material, the second tri-layer contact comprising a second metal oxide layer in contact with the second silicon dioxide layer;

wherein the first metal oxide layer is different than the second metal oxide layer.